Dynamic Impedance Adjustment in Semiconductor Data Output Drivers

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Solution Overview

Problem

Semiconductor memory devices face challenges in maintaining impedance matching across varying manufacturing processes, power voltage fluctuations, and temperature changes, leading to signal reflection and distortion issues.

Innovation Solution

The implementation of a semiconductor memory device with a data output driver comprising first and second drivers, each with transistors of different sizes, allows for the adjustment of impedance through calibration codes to ensure accurate impedance matching and stable data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If impedance matching is achieved using fixed impedance values, then signal reflection is reduced, but impedance matching cannot be maintained across varying manufacturing processes, power voltage, and temperature changes

Engineering Contradiction:
Improvesignal qualityVSAvoidimpedance adaptability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic impedance adjustment by dividing the output driver into first and second drivers with different transistor sizes, where the second driver can be selectively activated to adjust impedance values in real-time based on operating conditions such as temperature, voltage, and manufacturing variations

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the impedance parameter by controlling the activation state of the second driver relative to the first driver. By adjusting the ratio of activation between these two drivers with different transistor sizes, the overall output impedance can be dynamically tuned to match the transmission line impedance under varying operating conditions

Inventive Principle:
Principle #35Parameter changes

2Reliability

If ZQ calibration logic is used to adjust impedance, then signal quality is improved, but the data input/output period may be compromised due to calibration overhead

Engineering Contradiction:
Improvesignal qualityVSAvoiddata input/output speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs impedance calibration in advance during the initialization phase, determining the optimal activation ratio between the first and second drivers before actual data operations begin. This preliminary calibration ensures that impedance matching is established beforehand, allowing subsequent data I/O operations to proceed at full speed without interruption for recalibration

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If a single driver configuration is used, then device complexity is reduced, but impedance adjustment capability is limited

Engineering Contradiction:
Improvedriver structureVSAvoidimpedance adjustment range
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent segments the output driver into multiple independent driver units (first driver and second driver), each with different transistor sizes. This segmentation allows each driver to contribute differently to the overall output, enabling fine-grained impedance adjustment by selectively activating or deactivating specific driver segments based on the required impedance level

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10529393B2Semiconductor device and method of operating and controlling a semiconductor device
Publication Date: 2020.01.07 SAMSUNG ELECTRONICS CO LTD
  • US10529393B2 patent drawing
  • US10529393B2 patent drawing
  • US10529393B2 patent drawing

AI summary

An exemplary embodiment includes a method of controlling a semiconductor device. The semiconductor device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, a row decoder for receiving a row address and selecting a word line corresponding to the row address, a column decoder for receiving a column address and selecting a bit line corresponding to the column address, a sense amplifier for reading data stored in a memory cell connected to the selected word line and the selected bit line, and a data output driver. The method includes setting a calibration code for a driver control code, to control an initial current strength of the data output driver, and changing the calibration code to change the driver control code during a read or write operation for the memory cell array.