Dynamic Address Mapping in Disaggregated Memory Pools
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Solution Overview
Problem
Disaggregated memory architectures in computing systems face increased latency and suboptimal performance due to high remote memory access penalties, with current solutions relying on CPU caches and static memory allocation methods that limit scalability and efficiency.
Innovation Solution
Implementing a software-driven dynamic memory allocation technique using memory pooling circuitries (MPCs) with a translation lookaside buffer (TLB) to dynamically allocate and deallocate memory addresses across multiple CPUs, optimizing memory utilization and reducing latency through non-contiguous memory distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If disaggregated memory architecture is used to increase memory capacity and utilization, then memory utilization is improved, but access latency increases significantly
Solution Approach 1:
The system performs preliminary actions by pre-fetching memory data before it is actually needed. The memory controller monitors access patterns and proactively retrieves data from disaggregated memory into local caches or buffers, so that when the CPU needs the data, it is already available locally, thereby reducing access latency while maintaining high memory utilization
Solution Approach 2:
The patent introduces intermediate buffering layers (such as memory pooling circuitries and translation lookaside buffers) between the CPU and disaggregated memory. These intermediaries cache frequently accessed data and manage address translations, reducing the direct access latency to remote memory while enabling efficient utilization of large disaggregated memory pools
2Device complexity
If static memory allocation is used to simplify memory management, then device complexity is reduced, but scalability and performance are limited
Solution Approach 1:
The system implements dynamic memory allocation where memory regions are not fixed but can be reallocated based on runtime conditions. The memory controller dynamically adjusts address mappings and memory region assignments in response to changing workload demands, enabling the system to scale efficiently while maintaining relatively simple management through automated adaptation rather than complex manual configuration
Solution Approach 2:
The patent employs parameter changes by dynamically modifying memory address space parameters (such as base addresses, region sizes, and mapping configurations) based on system state. This allows the memory management system to adapt to different workload scenarios and scale accordingly without requiring fundamental changes to the memory architecture or management complexity
3Speed
If CPU caches are used to reduce remote memory access latency, then access speed is improved, but memory utilization and scalability are limited
Solution Approach 1:
The system merges the benefits of CPU caches with disaggregated memory by creating a unified memory hierarchy. Local caches continue to provide fast access for frequently used data, while the memory pooling circuitry aggregates memory from multiple nodes into a large shared pool, combining the speed advantages of caching with the capacity advantages of disaggregation to achieve both high access speed and high memory utilization
Solution Approach 2:
The memory pooling circuitry performs multiple functions: it acts as a cache for frequently accessed data (providing fast access like CPU caches), manages address translations for disaggregated memory (enabling scalability), and coordinates memory allocations across multiple nodes (improving utilization). This multi-functionality allows the system to achieve cache-like performance without sacrificing memory utilization or scalability
Data Source
AI summary
The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs). The LMAs are to be processed by one or more memory controllers (MCs) coupled to the one or more registers based on MC memory regions in each of the one or more MCs, the MC memory regions having a predetermined memory size granularity. At least some of the LMAs map to non-contiguous memory regions of the shared memory and of the one or more MCs.