Dynamic Memory Mode Switching for Error Correction
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Solution Overview
Problem
Conventional NAND type flash memory systems face challenges in maintaining data integrity due to increasing raw bit error rates (RBER) as the number of bits stored in each memory cell increases, leading to reduced storage capacity and efficiency over time.
Innovation Solution
A memory system with a nonvolatile memory, error correcting circuit, and memory controller that employs a variable-length coding system to adjust the coding rate based on error correction results, and changes the memory mode from a higher bit mode to a lower bit mode when the coding rate falls below a threshold, thereby reducing the number of levels and improving error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a higher bit mode (e.g., TLC, MLC) is used to store more bits per memory cell, then storage capacity increases, but raw bit error rate increases and data integrity deteriorates
Solution Approach 1:
The patent implements dynamic mode switching between different memory cell modes (SLC, MLC, TLC, QLC) based on real-time error correction performance. The controller monitors the coding rate after error correction and automatically transitions between modes to maintain optimal data integrity while maximizing storage capacity, making the system adaptable rather than static.
Solution Approach 2:
The patent changes the operational parameters of the memory cell by switching between different bit-per-cell modes (1-bit SLC, 2-bit MLC, 3-bit TLC, 4-bit QLC). This parameter change allows the system to adjust the balance between storage capacity and error rate dynamically, selecting the appropriate mode based on current error correction needs.
2Reliability
If a fixed high coding rate is used to maintain data integrity, then error correction capability improves, but storage efficiency decreases due to increased over-provisioned percentage
Solution Approach 1:
The patent employs dynamic coding rate adjustment based on the actual error correction performance. Instead of using a fixed high coding rate, the system adapts the coding rate in real-time based on the monitored error patterns and correction needs, optimizing the balance between data integrity and storage efficiency.
Solution Approach 2:
The patent implements a feedback mechanism where the controller monitors the coding rate result after error correction and uses this information to adjust future error correction operations. This closed-loop feedback allows the system to maintain appropriate error correction capability while minimizing the over-provisioned percentage and maximizing storage efficiency.
Data Source
AI summary
According to one embodiment, a memory system includes a memory, an error correcting circuit and a memory controller. The memory includes a memory cell which is writable in a memory mode including a first mode and a second mode. The first mode is a mode in which a value of bits is written to the memory cell. The second mode is a mode in which a value of bits smaller than that in the first mode is written to the memory cell. The memory controller controls a coding rate for the error correction on the basis of result of error correction. The controller sets the first mode as the memory mode to be used. The controller changes the memory mode to be used from the first mode to the second mode in a case where the coding rate is less than a first threshold.