Dynamic Memory Block Refresh Order for Data Retention
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Solution Overview
Problem
Memory devices face data retention issues due to varying data retention times of memory cells, leading to potential data loss and degradation, especially when internal or external factors like leakage currents or active-precharge operations of neighboring word lines affect the capacitors and transistors.
Innovation Solution
A memory device and system that dynamically change the order of memory block refresh operations during normal and target refresh operations, using a refresh controller to manage memory blocks differently based on their initial refresh timing and data retention needs, thereby reducing the time required for refresh operations and minimizing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are designed with a preset reference time for data retention, then the data retention time is sufficient for normal operation, but some memory cells still have data retention time less than the reference time due to internal or external factors
Solution Approach 1:
The patent applies local quality by identifying and separately handling memory cells with insufficient data retention time. Through sensing operations, the system detects which memory cells have retention times below the reference threshold and applies targeted refresh operations to those specific cells, rather than uniformly refreshing all memory cells. This localized approach ensures that problematic cells receive additional attention while maintaining overall system reliability.
2Ease of operation
If a fixed refresh interval is used based on reference time, then refresh operations are simple to manage, but memory cells with shorter retention times may still lose data
Solution Approach 1:
The patent implements dynamics by transitioning from a static, fixed refresh interval to a dynamic refresh strategy. The system continuously monitors data retention times of memory cells and adjusts refresh timing based on actual cell conditions. Memory cells with shorter retention times are refreshed more frequently, while cells with adequate retention follow the standard schedule. This dynamic adaptation ensures data integrity while optimizing refresh operation efficiency.
Solution Approach 2:
The patent employs feedback mechanisms by sensing the actual data retention time of memory cells and using this information to control subsequent refresh operations. The sensing operations provide feedback about which cells require additional refresh attention, and this feedback loop enables the system to adaptively adjust refresh timing to prevent data loss in vulnerable cells.
3Productivity
If all memory blocks are refreshed in a fixed sequence, then the refresh operation is straightforward, but the time required for refresh operations cannot be optimized
Solution Approach 1:
The patent applies preliminary action by performing sensing operations before the main refresh operation to identify which memory cells require refresh attention. This preliminary detection phase allows the system to prepare an optimized refresh sequence in advance, targeting only the necessary memory blocks with additional refresh cycles. By identifying problematic cells beforehand, the system can efficiently allocate refresh resources without disrupting the overall refresh timeline.
Data Source
AI summary
A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.