Dynamic Memory Sparing for DRAM Error Correction
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Solution Overview
Problem
The increasing density and operating speed of memory devices lead to higher runtime errors, despite the presence of error checking and correction (ECC) mechanisms. Existing solutions like sparing and overprovisioning increase costs and reduce reliability, availability, and serviceability (RAS) of DRAM devices.
Innovation Solution
A memory subsystem with dynamically allocated space for error correction and sparing, which includes error detection logic to dynamically allocate active memory device space for sparing, write a poison pattern into failed cache lines, perform permanent fault detection, and adjust ECC based on fault detection results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sparing resources are included in memory devices, then reliability is improved, but device cost increases due to overprovisioning
Solution Approach 1:
The patent implements dynamic sparing where spare memory resources are not permanently allocated but are instead dynamically assigned based on real-time error detection. When errors are detected in specific memory regions, the system dynamically remaps those regions to use spare resources, allowing the same physical resources to serve multiple purposes at different times.
Solution Approach 2:
The system changes the operational parameters of memory resources by adjusting the mapping between logical addresses and physical memory locations. When errors are detected, the system modifies address translation tables to redirect accesses away from failed regions to healthy spare regions, effectively changing how resources are utilized without adding physical overhead.
2Reliability
If overprovisioning is implemented at system level, then system error mitigation is improved, but system cost increases due to additional memory devices
Solution Approach 1:
The patent merges the functions of data storage and error mitigation into a single memory subsystem. Instead of having separate dedicated spare memory devices, the system combines available memory resources and dynamically allocates them for both data storage and error correction purposes, eliminating the need for additional dedicated ECC memory devices.
Solution Approach 2:
The patent makes memory resources universal by allowing them to serve multiple functions. The same memory regions that store user data can also serve as spare resources for error mitigation when needed, eliminating the need for dedicated single-function spare memory devices.
3Reliability
If traditional ECC is applied, then error correction capability is improved, but the frequency of errors can still exceed correction measures
Solution Approach 1:
The system performs preliminary error detection and remapping actions before errors can propagate or cause system failure. By continuously monitoring memory regions and pre-remapping problematic areas to spare regions, the system prevents error accumulation that would otherwise exceed ECC correction capacity.
Solution Approach 2:
The patent implements feedback mechanisms where error detection results directly trigger remapping actions. The system continuously monitors memory health and dynamically adjusts resource allocation based on real-time error patterns, allowing it to adapt to increasing error frequencies without requiring proportional increases in ECC overhead.
Data Source
AI summary
A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.