Dynamic Power Scaling for Volatile Memory Noise Tolerance

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Solution Overview

Problem

Volatile memory technologies face challenges in power consumption and noise tolerance, particularly in machine learning applications where deep learning algorithms exhibit varying noise immunity across processing layers, leading to inefficiencies in power usage and potential bit errors.

Innovation Solution

Implementing selective noise tolerance modes of memory operation that dynamically adjust input power levels based on the noise tolerance level of the workload, using a multi-level power supply to optimize power consumption and reduce bit errors by varying input voltage and current levels across different memory banks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If continuous power is supplied to volatile memory to maintain data, then data retention is ensured, but power consumption increases

Engineering Contradiction:
Improvedata retentionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic power management by adjusting power supply levels to memory based on the noise tolerance requirements of different workload types. Instead of continuous full-power supply, the system dynamically scales power consumption according to actual needs, reducing overall power usage while maintaining data retention when required

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters by varying power supply levels and memory refresh rates based on workload characteristics. For workloads with high noise tolerance, lower power levels and reduced refresh rates are used, while critical workloads receive higher power levels, optimizing the balance between data retention and power consumption

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If high power levels are used in volatile memory, then noise tolerance improves, but power consumption increases

Engineering Contradiction:
Improvenoise toleranceVSAvoidpower consumption
Core Design Contradiction:
Object-affected harmful factorsVSUse of energy by moving object

Solution Approach 1:

The patent applies different power levels to different memory banks or memory regions based on the specific noise tolerance requirements of the workload being executed. Instead of uniformly high power across all memory operations, localized power adjustment is implemented where only necessary memory regions receive high power levels, reducing overall power consumption while maintaining adequate noise tolerance

Inventive Principle:
Principle #3Local quality

3Reliability

If memory refresh operations are performed frequently, then data integrity is maintained, but performance and power efficiency deteriorate

Engineering Contradiction:
Improvedata integrityVSAvoidperformance efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system implements periodic memory refresh operations with variable intervals based on workload characteristics and memory state. Instead of fixed frequent refreshes, the refresh period is dynamically adjusted - extending intervals when data integrity risk is low and shortening them when needed, thereby improving performance efficiency while maintaining data integrity

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The memory system incorporates self-refresh capabilities where memory can perform refresh operations autonomously during idle periods or low-activity states without impacting main workload performance. This self-service approach allows refresh operations to occur in background timing windows, maintaining data integrity without degrading overall system productivity

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP3382565B1Selective noise tolerance modes of operation in a memory
Publication Date: 2019.10.23 INTEL CORP
  • EP3382565B1 patent drawingFigure 1~3b
  • EP3382565B1 patent drawingFigure 4
  • EP3382565B1 patent drawingFigure 5~13

AI summary

In one embodiment, a system employing selective noise tolerance modes of memory operation in accordance with one aspect of the present description can reduce levels of memory operation power consumption as compared to those achieved by many prior devices. In one embodiment, each noise tolerance mode has an associated level of input power to a memory. For example, in one embodiment, the greater the degree of tolerance for noise in the data of a workload being processed, the greater the reduction in memory input power and the greater the resultant reduction in power consumption. Other aspects and advantages are described.