Power Supply For Data Processing TRIZ Cases
- Industrial Personal Computer Stacked Housing UPS Integration
Stacked housing modules connect via a vertical bus to integrate an uninterruptible power supply within the industrial personal computer chassis.
- Custom Keyboard API Segmentation for Display Behavior
An application programming interface segments user interface objects to decouple visual appearance from operating system display behavior.
- Charge Management for Multicore Processor Voltage Stability
A charge management system translates core activity into digital power proxy data to dynamically adjust processor throttle states.
- Dynamic Power Scaling for Volatile Memory Noise Tolerance
A memory system adjusts input voltage and current levels to reduce active leakage while maintaining required data retention.
- SERDES PHY Data Scrambling for Power Reduction
A SERDES PHY scrambles data using a control signal to enable clock gating.
- SSD Controller Power-Off Duration Estimation
A storage controller estimates power-off duration from memory error rates to adjust read levels for rapid data recovery.
- Processor Frequency Scaling via Touch Gesture Hints
Touch gesture hints trigger dynamic clock frequency scaling in the processor governor, reducing response lag and battery drain during user interactions.
- Dual Processing System for Wearable Power Management
A dual processing system divides tasks between a low-power microcontroller and a high-performance processor to manage wearable device operations.
- Power Hold-Off Circuit for Abrupt Power Loss in BGA SSDs
A power hold-off circuit manages energy transfer between battery and capacitors using step-up and step-down regulators.
- Low-Voltage Interrupt Sleep Mode for Portable Electronic Devices
Processor enters sleep mode via low-voltage interrupt, avoiding shutdown and eliminating booting time after charging.
- Replica Path Timing Normalization for Adaptive Voltage Scaling
Normalizing replica path delays determines optimal processor frequency and voltage, avoiding worst-case limits that restrict performance.
- Processor Slew Rate Control for Battery Voltage Droop Prevention
Adjusting processor slew rates according to battery charge state prevents voltage droop and system shutdown during high power demand.
- Dynamic Sleep Transistor Sizing for Leakage Power Reduction
A power control unit dynamically adjusts sleep transistor size to maintain memory retention levels.
- Dynamic Power Cap Adjustment for Computing System Stability
A baseboard management controller adjusts power caps to prevent system shutdowns.
- Negative Bit Line Driver Circuitry for Memory Yield
Capacitive pulse circuitry drives the time-varying ground voltage below zero volts, improving write margins and increasing die yield in dual-port memory cells.