SERDES PHY Data Scrambling for Power Reduction
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Solution Overview
Problem
High-speed serial links face challenges in power consumption due to the need for data scrambling, which is not supported by public protocols near serializer/deserializer (SERDES) input/output ports, and may require more chiplet interconnections in future ASIC applications.
Innovation Solution
A mechanism is introduced that allows data scrambling and descrambling using a non-scrambled header/pattern and a linear feedback shift register (LFSR) at any point on the data transmission path, enabling power savings by using non-scrambled data where possible and implementing clock gating, with SERDES PHY circuits handling scrambling and descrambling operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data scrambling is implemented near SERDES input/output ports in high speed serial links, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent extracts the data scrambling function from the SERDES peripheral and relocates it to the IP core. This separation allows the SERDES to operate independently without the power consumption penalty of continuous scrambling operations, while maintaining transmission reliability through IP-level scrambling when needed.
Solution Approach 2:
The patent implements dynamic control of scrambling operations through a control signal that enables or disables scrambling based on transmission requirements. This dynamic approach allows the system to maintain reliability when scrambling is needed while reducing power consumption during periods when scrambling can be omitted.
2Reliability
If data scrambling is implemented for future ASIC chiplet interconnections, then data transmission security is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal scrambling mechanism within the IP core that can serve multiple functions: data security, error detection, and compatibility with future ASIC chiplet interconnections. This multi-functional approach avoids the need for separate dedicated scrambling hardware for each purpose, thereby reducing overall device complexity.
Solution Approach 2:
The patent introduces a control signal as an intermediary mechanism that coordinates between the IP core scrambling function and the SERDES transmission function. This control signal acts as a mediator that enables or disables scrambling based on transmission requirements, simplifying the interaction between components and reducing implementation complexity.
3Use of energy by moving object
If non-scrambled data is transmitted to enable power savings, then power consumption is reduced, but data transmission reliability may deteriorate
Solution Approach 1:
The patent employs dynamic control of the scrambling function through a control signal that adapts to transmission requirements. The system can switch between scrambled and non-scrambled modes based on the specific transmission scenario, enabling power savings when reliability requirements allow non-scrambled transmission while maintaining reliability when needed.
Solution Approach 2:
The patent changes the operational parameter of the scrambling function from a fixed state to a variable state controlled by a control signal. This parameter change allows the system to adjust between scrambled and non-scrambled modes, optimizing the balance between power consumption and transmission reliability based on actual transmission requirements.
Data Source
AI summary
A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.