Replica Path Timing Normalization for Adaptive Voltage Scaling
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Solution Overview
Problem
Conventional methods for determining the maximum clock frequency and supply voltage for processors are expensive, time-consuming, and often set to 'worst-case' values, which can unnecessarily limit processor performance due to variations in process and operating conditions, as they rely on testing critical paths in test chips that may not accurately represent the actual processor's critical paths.
Innovation Solution
The use of replica paths within the processor to determine operating frequency and voltage by normalizing delays, adjusting for variations in reference voltages, and masking specific paths to improve accuracy, allowing for individualized settings based on the processor's specific conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used to determine maximum clock frequency and supply voltage, then reliability is ensured, but development time and cost increase significantly
Solution Approach 1:
The patent creates replica paths that are copies of the actual critical paths in the processor. These replica paths are simpler to test and can be used to determine timing margins without testing the full processor at all operating conditions, thereby reducing testing time while maintaining reliability.
Solution Approach 2:
The patent segments the complex timing analysis by creating separate replica paths for different functional modules. Each replica path independently represents a specific module's critical path, allowing parallel testing and analysis of multiple modules without testing the entire processor simultaneously.
2Reliability
If worst-case values are used to ensure proper operation, then reliability is maximized, but processor performance is unnecessarily limited
Solution Approach 1:
The patent applies local quality by determining timing margins specifically for each functional module's replica path under actual operating conditions. Instead of using a single conservative worst-case value for the entire processor, each module gets optimized timing parameters based on its specific characteristics and operating environment.
Solution Approach 2:
The patent enables dynamic adjustment of clock frequency and supply voltage for each functional module based on its actual timing margins and operating conditions. This replaces static worst-case values with dynamic, condition-based parameters that optimize performance while ensuring reliability.
3Device complexity
If replica paths are used to represent circuit paths, then testing complexity is reduced, but accuracy of timing margin determination may be compromised
Solution Approach 1:
The patent incorporates feedback by adjusting the replica path delays based on actual measured timing margins from the processor. The replica paths are used to predict timing behavior, and these predictions are validated against actual measurements, with adjustments made to improve accuracy of timing margin determination.
Solution Approach 2:
The patent uses parameter changes by varying the delay values in replica paths to match actual timing conditions. By adjusting replica path delays to correspond to different operating conditions and comparing these against actual processor timing measurements, accurate timing margins are determined despite the simplified replica structure.
Data Source
AI summary
A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.