Negative Bit Line Driver Circuitry for Memory Yield
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Solution Overview
Problem
Dual-port memory cells in integrated circuits face challenges in reliable operation due to increased PVT variations and reduced read/write margins at lower power supply voltages, as existing techniques to adjust power supply levels are not applicable, affecting memory yield.
Innovation Solution
The implementation of a dual-port memory cell design with a time-varying power supply voltage that is temporarily lowered during write operations, using adjustable power supply circuitry including a programmable pulse generator and tunable capacitive circuitry to optimize voltage drop, ensuring successful writes while maintaining normal operation at ground voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory cell power supply voltage is temporarily raised during read operations to enhance read stability, then read stability is improved, but write ability deteriorates
Solution Approach 1:
The patent segments the power supply control into separate pathways for read and write operations. The read path raises power supply voltage to enhance read stability, while the write path maintains normal voltage to preserve write ability. This is achieved through separate control logic that selectively activates read enhancement circuitry without interfering with write operations.
Solution Approach 2:
The patent applies local quality by selectively adjusting power supply voltage only in specific circuit regions during read operations, rather than globally affecting the entire memory array. The write circuits operate with normal power supply characteristics, ensuring write ability is not compromised while read stability is enhanced in the targeted region.
2Use of energy by moving object
If lower power supply voltages are used to reduce power consumption, then power consumption is reduced, but read/write margins deteriorate
Solution Approach 1:
The patent implements dynamic power supply voltage adjustment that adapts to operational requirements. During normal operation, lower power supply voltages are used to reduce power consumption. During read operations, the power supply voltage is dynamically raised to restore read margins. This dynamic adjustment allows the system to operate at low power while maintaining adequate read/write margins when needed.
Solution Approach 2:
The patent changes the power supply voltage parameter selectively based on operational mode. The system transitions between low voltage operation (for power savings) and elevated voltage operation (for read stability). This parameter change is controlled through detection circuitry that monitors operational state and adjusts voltage accordingly, allowing the memory to achieve both low power consumption and adequate read/write margins.
3Area of moving object
If transistor sizes are scaled down to increase integration density, then integration density is improved, but read/write margins and yield deteriorate
Solution Approach 1:
The patent implements a universal power supply adjustment mechanism that benefits all scaled transistors uniformly. The read enhancement circuitry compensates for the reduced margins inherent in scaled devices, allowing the memory array to maintain adequate read/write margins despite transistor scaling. This universal approach preserves yield across the entire array while enabling high integration density through scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances write performance and increases die yield by optimizing the voltage drop during write operations, thereby improving the reliability and efficiency of dual-port memory cells.
Implementation Method 1
The time-varying power supply voltage may be generated on a control line using adjustable power supply circuitry. The adjustable power supply circuitry may include at least a programmable pulse generator, a tunable capacitive circuitry, and a shorting transistor.
Data Source
AI summary
Integrated circuits with memory elements are provided. Data may be loaded into the memory elements using write driver circuitry. The write driver circuitry may be provided with a fixed positive power supply voltage and an time-varying ground power supply voltage that is less than the positive power supply voltage. The time-varying ground power supply voltage may be generated using programmable power supply circuitry. The programmable power supply circuitry may include a pulse generation circuit and a configurable capacitive circuit. The pulse generation circuit may output a pulse signal to the capacitive circuit. In response to receiving the pulse signal, the capacitive circuit may push the time-varying ground power supply voltage to a negative value. The time-varying ground power supply voltage may be driven below zero volts for at least a portion of a write cycle to help improve write margins and increase memory yield.