Dynamic Sleep Transistor Sizing for Leakage Power Reduction
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Solution Overview
Problem
As process technologies scale, transistor leakage increases, leading to higher power consumption, especially at varying operating voltages, where existing sleep transistor designs become inefficient, resulting in increased leakage power consumption in devices like SRAM cells.
Innovation Solution
An apparatus with a power control unit (PCU) dynamically adjusts the size of the sleep transistor to maintain the power supply to memory cells just above the retention power supply level, using a look-up table to determine the appropriate transistor size based on the operating voltage, thereby reducing leakage power across a wide voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sleep transistor size is optimized for a particular operating voltage, then data retention reliability is improved at that voltage, but leakage power increases at higher operating voltages
Solution Approach 1:
The patent implements a dynamically adjustable sleep transistor configuration where multiple sleep transistors can be selectively enabled or disabled based on the operating voltage level. This allows the system to transition from a static to a dynamic configuration, optimizing both data retention and leakage power at different voltage conditions.
Solution Approach 2:
The system changes the effective transistor size parameter by selectively enabling different numbers of parallel sleep transistors based on operating voltage. At higher voltages, more transistors are enabled to increase the effective W/L ratio and reduce leakage, while at lower voltages, fewer transistors are enabled to maintain data retention reliability.
2Loss of energy
If the sleep transistor W/L ratio is increased to reduce leakage at higher voltages, then leakage power is reduced, but data retention failures occur at minimum operating voltage
Solution Approach 1:
The sleep transistor is divided into multiple segmented transistors connected in parallel, each with a smaller individual W/L ratio. By selectively enabling different segments based on operating voltage, the system achieves an effective high W/L ratio at high voltages without requiring any single transistor to have an excessively large size that would cause data retention failures at minimum voltage.
3Device complexity
If a fixed sleep transistor size is used across all operating voltages, then device complexity is reduced, but power consumption efficiency deteriorates across the voltage range
Solution Approach 1:
The patent creates a universal sleep transistor configuration that can adapt to multiple operating voltage conditions. By using parallel transistors with control logic that selectively enables them based on voltage detection, a single circuit structure serves multiple functions: maintaining data retention at low voltage and minimizing leakage at high voltage, eliminating the need for different designs for different voltage ranges.
Data Source
AI summary
Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.