Dynamic Pull-Up Weakening for Memory Write Assist
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Solution Overview
Problem
Volatile memory elements in integrated circuits face challenges with decreased read and write margins due to lower power supply voltages and smaller device sizes, affecting reliable operation.
Innovation Solution
The implementation of a pull-up weakening control circuit that dynamically adjusts the power supply voltage to improve write margins without affecting read performance, using a single p-channel transistor shared among memory cells in a column and a control signal that is driven to ground during read operations and temporarily adjusted during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If lower power supply voltages are used to scale down integrated circuits, then power consumption is reduced and device size is decreased, but read and write margins for volatile memory elements deteriorate
Solution Approach 1:
The pull-up transistor's resistance is dynamically adjusted based on operation mode: during write operations, the resistance is increased to weaken the pull-up effect and facilitate data writing, while during read operations, the resistance is decreased to strengthen the pull-up effect and ensure stable read margins. This dynamic adjustment allows the memory cell to maintain reliable operation at lower supply voltages.
Solution Approach 2:
The invention changes the resistance parameter of the pull-up transistor by controlling its gate voltage through the pull-up control circuit. By varying the resistance value according to whether a write or read operation is being performed, the system optimizes the noise margins for each operation type while enabling operation at reduced supply voltages.
2Area of moving object
If device sizes are reduced to increase integration density, then more memory cells can be packed into the same area, but read and write margins for volatile memory elements deteriorate
Solution Approach 1:
The dynamic control of the pull-up transistor resistance compensates for the reduced noise margins inherent in scaled-down device sizes. By adjusting the resistance during write operations to weaken the pull-up effect, the circuit maintains adequate write margins even in smaller, more densely integrated memory cells.
3Area of moving object
If a single p-channel transistor is shared among multiple memory cells in a column, then device area is reduced and integration density is increased, but control complexity for maintaining read performance while improving write margins increases
Solution Approach 1:
The single pull-up transistor serves multiple memory cells in a column, and the pull-up control circuit generates a unified control signal that applies to all shared transistors. This multi-functional approach allows one control circuit to manage multiple transistors, reducing overall device area while maintaining the ability to optimize write margins without compromising read performance.
Data Source
AI summary
Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access transistors, and optionally a separate read port. The cross-coupled inverters in each memory cell may have a positive power supply terminal. The positive power supply terminal of each memory cell along a given column in the array may be coupled to a corresponding pull-up transistor. The pull-up transistor may receive a control signal from a pull-up weakening control circuit. The control signal may be temporarily elevated during write operations and may otherwise be driven back down to ground to help optimize read performance. The pull-up weakening control circuit may be implemented using a chain of n-channel transistors or a resistor chain.