Dynamic Register with Data-Dependent Hold Time
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Solution Overview
Problem
Traditional register circuits in pipeline systems introduce significant delays due to setup and hold time requirements, which constrain the speed of logic evaluation circuits and are often mitigated by using pulsed clock signals, but these solutions increase hold time requirements and complexity.
Innovation Solution
An inverting dynamic logic register with a complementary pair of evaluation devices, delay logic, latching logic, and a keeper circuit that reduces hold time requirements by shortening the delay between the clock and kill signals based on the logic function's state, eliminating the need for pulsed clock signals and providing zero setup time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional register circuits are used in pipeline systems, then reliable data latching is achieved, but significant delays are introduced due to setup and hold time requirements
Solution Approach 1:
The patent implements dynamic logic circuits where the hold time requirement becomes data-dependent rather than fixed. The hold time is shortened when the logic function evaluates to a first state (e.g., logic 0) and lengthened when it evaluates to a second state (e.g., logic 1), allowing the circuit to adapt its timing requirements based on the actual data being latched.
Solution Approach 2:
The invention changes the parameter of hold time from a fixed value to a variable value that depends on the logic function's output state. This is achieved through data-dependent timing mechanisms that adjust the hold time requirement based on whether the logic function evaluates to a first or second state, thereby optimizing the speed-performance of the pipeline system.
2Loss of time
If pulsed clock signals are used to reduce hold time requirements, then hold time is reduced, but circuit complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for complex pulsed clock signal generation circuits by implementing data-dependent hold time reduction through the logic function's own output state. The hold time is dynamically adjusted based on the logic function evaluation, removing the requirement for separate pulsed clocking mechanisms and their associated complexity.
3Productivity
If setup time requirements are reduced to increase pipeline speed, then operating speed increases, but data stability requirements become more stringent
Solution Approach 1:
The patent applies dynamic timing where both setup and hold time requirements become data-dependent. The setup time and hold time are adjusted based on the logic function's output state, allowing the circuit to relax timing constraints when the logic function evaluates to a first state while maintaining reliability when it evaluates to a second state.
Data Source
AI summary
Dynamic logic register including evaluation logic, delay logic, latching logic, and a keeper circuit. The evaluation logic evaluates a logic function based on data input. The logic function evaluates to either a first state or a second state. The delay logic generates a kill signal, where the kill signal is a delayed version of a clock signal, and where the delay between the clock and kill signals comprises a hold time, and where the hold time is shortened when the logic function evaluates to the first state. The latching logic is responsive to the clock and kill signals and the state of pre-charged node, and controls the state of an output node based on the state of a pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of the kill signal, and otherwise presents a tri-state condition to said output node.