Dynamic Threshold Transistor Fabrication via Void Burial
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Solution Overview
Problem
MOS transistors with conventional structures suffer from degraded operational speed due to parasitic capacitance and increased leakage current, primarily caused by the p/n junction, and existing methods introduce crystal defects and surface damage during the epitaxial growth of silicon layers on SiGe mixed crystal layers.
Innovation Solution
A fabrication method that uses a bulk silicon substrate without processing for the channel region, involving ion implantation, epitaxial growth of SiGe mixed crystal layers, selective etching to form voids, and burying them with insulation films, while maintaining the surface flatness to avoid defects and positional errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p/n junction is formed to isolate source/drain regions from the well, then device isolation is achieved, but parasitic capacitance increases and operational speed degrades
Solution Approach 1:
The patent removes the p/n junction structure entirely by forming source and drain regions directly in the bulk silicon substrate without a separate well layer. This extraction of the problematic junction interface eliminates the parasitic capacitance while maintaining device isolation through alternative means such as oxidation isolation or physical separation of doped regions.
Solution Approach 2:
The patent applies different doping conditions to different regions of the bulk silicon substrate. Source and drain regions are locally doped with high concentration to create low-resistance contacts, while the channel region maintains the intrinsic bulk silicon quality. This local differentiation achieves isolation and low capacitance without requiring a global p/n junction structure.
2Ease of manufacture
If epitaxial growth is used to form silicon layers on SiGe mixed crystal layers, then device structure is created, but crystal defects and surface damage are introduced
Solution Approach 1:
The patent extracts the SiGe mixed crystal layer from the device structure, using it only as a sacrificial mask during fabrication. The final device is formed entirely in the bulk silicon substrate, eliminating the interface between SiGe and silicon that causes crystal defects. The SiGe layer is removed after serving its masking function, leaving a defect-free bulk silicon device.
Solution Approach 2:
The SiGe mixed crystal layer is formed preliminarily as a patterned mask before the main device fabrication. This preliminary structure guides the doping and processing steps, then is removed after completing its masking function. This preliminary action enables precise device formation without the SiGe layer remaining in the final structure to cause defects.
3Reliability
If source and drain regions are formed in a well structure, then device isolation is achieved, but leakage current increases
Solution Approach 1:
The patent removes the well structure that causes leakage current by forming source and drain regions directly in the bulk silicon substrate. The problematic p/n junction interfaces inherent in well-based structures are extracted, eliminating the leakage pathways while maintaining isolation through alternative methods such as oxidation barriers or physical separation.
Solution Approach 2:
The patent uses a composite approach combining bulk silicon substrate with localized doped regions. The bulk silicon provides low-leakage properties, while localized phosphorus or boron doping creates the necessary source and drain regions. This composite structure achieves isolation and low leakage without requiring a separate well layer that would introduce leakage paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces junction capacitance, minimizes leakage current, and maintains the high crystal quality of the bulk silicon substrate, improving the operational characteristics and reducing variations in device performance.
Implementation Method 1
filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon
Implementation Method 2
removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer
Implementation Method 3
ion implantation, epitaxial growth of SiGe mixed crystal layers
Data Source
AI summary
A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.