Dynamic Via Pillar Sizing for Electromigration Compliance

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Solution Overview

Problem

Conventional automatic placement and routing (APR) processes use wide output pins to meet electromigration rules, leading to excessive layout area consumption and interference with nearby routing tracks, as well as overdesign in cells with light driving loads due to fixed-shaped pins.

Innovation Solution

A system that dynamically determines the layout pattern for via pillar structures based on the driving load of cells, using a processor to select the minimum-sized pattern that meets the electromigration rule, allowing for efficient use of layout area and preventing overdesign.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wide output pins are used to meet electromigration rules, then reliability is improved, but layout area increases and routing track interference occurs

Engineering Contradiction:
Improveelectromigration rule complianceVSAvoidlayout area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by making the output pin width variable rather than uniform. Different cells with different driving loads are assigned different pin widths - cells with heavy driving loads use wider pins to meet electromigration rules, while cells with light driving loads use narrower pins. This localized adaptation resolves the contradiction by providing sufficient reliability only where needed, thereby reducing overall layout area and minimizing routing track interference.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of output pin width from a fixed value to a variable parameter that adapts to different driving load conditions. By dynamically adjusting the pin width parameter based on the specific requirements of each cell, the system achieves electromigration compliance for high-current cells while using minimal width for low-current cells, thus resolving the area-reliability tradeoff.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If fixed-shaped wide pins are used in all cells to meet electromigration rules, then reliability is improved, but layout area is wasted due to overdesign in cells with light driving loads

Engineering Contradiction:
Improveelectromigration rule complianceVSAvoidlayout area waste
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent implements local quality by assigning different pin widths to different cells based on their driving load characteristics. Instead of applying a uniform wide pin design to all cells, the system evaluates each cell's current requirements and assigns the minimum necessary pin width. This prevents overdesign in light-load cells, eliminating layout area waste while maintaining reliability where actually needed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies partial action by providing electromigration protection only to the extent necessary for each cell. Rather than applying excessive wide pin design universally, the system provides just enough pin width to meet electromigration requirements for each specific cell's driving load. This partial application of the design rule eliminates unnecessary area consumption in cells that don't require full protection.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11727185B2System for designing semiconductor device
Publication Date: 2023.08.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11727185B2 patent drawing
  • US11727185B2 patent drawing
  • US11727185B2 patent drawing

AI summary

A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.