Dynamic Voltage Scaling for Leakage Reduction in SoC Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Static leakage power consumption poses a significant challenge in very large scale system-on-a-chip (SoC) integrated circuits, particularly in handheld devices, as it increases with finer geometry manufacturing processes, making it difficult to meet chip leakage targets using traditional power reduction techniques.
Innovation Solution
A data processing system employing dynamic voltage scaling and a drowsy voltage regulator to manage power supply voltages, ensuring the voltage difference between the memory's power supply terminals is maintained above the minimum state retention voltage to prevent data loss, while reducing leakage current by adjusting the voltage levels during low power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the ground terminal voltage of memory is increased above ground during low power mode to reduce leakage current, then leakage current is reduced, but the voltage difference across the memory may fall below the minimum state retention voltage causing data corruption
Solution Approach 1:
The patent implements dynamic voltage scaling by providing multiple regulated power supply terminals (VDD1, VDD2, VDD3) that can be independently adjusted to different voltage levels. The system dynamically selects and switches between different combinations of these terminals based on the desired power mode, allowing the voltage difference across the memory to be maintained above the minimum retention threshold while still achieving leakage reduction in low-power modes.
Solution Approach 2:
The patent changes the voltage parameters of the power supply terminals to different discrete levels (VDD1 > VDD2 > VDD3) to achieve both leakage reduction and data retention. By carefully selecting which terminals to activate and at what voltage levels, the system can adjust the effective voltage across the memory to balance between power consumption and reliability requirements.
2Loss of energy
If traditional power reduction techniques are used to meet chip leakage targets, then leakage current is reduced, but the techniques become insufficient as transistor leakage currents increase with finer geometry manufacturing processes
Solution Approach 1:
The patent segments the single power supply into multiple regulated power supply terminals (first, second, and third regulated power supply terminals) that can be independently controlled. This segmentation allows different voltage levels to be applied to different parts of the system or to the same memory at different times, enabling fine-grained power management that adapts to varying leakage conditions in different process geometries.
Solution Approach 2:
The multiple regulated power supply terminals serve multiple functions: they can operate individually or in combination, support different power reduction modes (ground lifting, voltage scaling), and adapt to various manufacturing process geometries. This multi-functionality makes the power reduction technique universally applicable across different process nodes and leakage scenarios.
3Use of energy by moving object
If the voltage difference across memory is reduced to lower power consumption, then power consumption is reduced, but data integrity may be compromised
Solution Approach 1:
The system dynamically adjusts the voltage difference across the memory by selectively activating different combinations of regulated power supply terminals. During active modes, the full voltage difference is applied for optimal performance and data integrity. During low-power modes, the system transitions to using fewer terminals or lower voltage levels while maintaining the voltage difference above the minimum retention threshold, thus achieving power reduction without compromising data integrity.
Data Source
AI summary
A method is provided for operating a data processing system having a memory. The memory is coupled between a first power supply voltage terminal for receiving a first variable potential and a second power supply voltage terminal for receiving a second variable potential. An initial difference between the first variable potential and the second variable potential is not less than a first voltage. The method comprises: receiving a command to transition the data processing system from a first power supply voltage to a second power supply voltage; changing the second variable potential so that a difference between the second variable potential and the first variable potential is greater than the first voltage; and after changing the second variable potential, changing the first variable potential, wherein a difference between the first variable potential and the second variable potential is not less than the first voltage.