Dynamic Wordline Tracking for Memory Power Optimization
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Solution Overview
Problem
Current compiler memory tracking schemes provide unnecessary power consumption by tracking the worst-case access time for all memory rows, leading to excessive discharge of bitlines and sense amplifiers during accesses with shorter paths, resulting in inefficient power usage and longer memory access times.
Innovation Solution
Implementing a dynamic tracking scheme that varies the duration of the asserted wordline based on the specific row being accessed, using dummy cells to simulate delays and adjust tracking signals dynamically, thereby reducing unnecessary discharges and optimizing access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If compiler memory tracking uses worst-case access time for all rows, then reliability is improved, but power consumption increases
Solution Approach 1:
The memory array is divided into multiple segments or regions with different access time characteristics. Instead of applying a uniform worst-case margin to all rows, the tracking system segments rows by their actual access time profiles, allowing differential margin application where shorter-path rows receive reduced margins and longer-path rows receive full margins, thus resolving the contradiction between reliability and power consumption.
Solution Approach 2:
The tracking system transitions from a static worst-case margin approach to a dynamic margin adjustment mechanism. The margin applied to each row is dynamically adjusted based on the actual access time characteristics of that specific row, enabling the system to maintain reliability for critical rows while reducing power consumption for non-critical rows with shorter access paths.
2Reliability
If worst-case margin is applied to all rows, then reliability is improved, but memory access time increases
Solution Approach 1:
Rows are segmented into different categories based on their access time characteristics. Critical rows that require worst-case margins are identified and treated differently from non-critical rows with shorter access paths. This segmentation allows the system to apply margins only where necessary, preventing unnecessary access time extensions for rows that don't require them.
Solution Approach 2:
Different margin qualities are applied to different regions or rows within the memory array. Instead of a uniform margin approach, each row receives a margin level appropriate to its specific access time characteristics, ensuring that reliability is maintained locally where needed while avoiding time penalties in regions where shorter access times can be achieved.
3Reliability
If bitlines and sense amplifiers discharge fully for worst-case tracking, then reliability is improved, but power consumption increases
Solution Approach 1:
The discharge level of bitlines and sense amplifiers is dynamically adjusted based on the actual access time requirements of the specific row being accessed. Instead of always discharging to the worst-case level, the system dynamically modulates the discharge amount, maintaining sufficient voltage margins for reliable operation while minimizing unnecessary energy dissipation in rows with shorter access paths.
Data Source
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AI summary
A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.