Semiconductor Memory Device ECC-Based Adaptive Refresh Control
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Solution Overview
Problem
As semiconductor memory devices, such as DRAM, become smaller, bit error rates increase, necessitating a more robust error correction code (ECC) operation to maintain data integrity and reliability.
Innovation Solution
A semiconductor memory device that adjusts refresh operations based on error information obtained through ECC decoding, increasing the number of refresh operations in memory cell rows with high error occurrence counts to enhance data retention and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of DRAM devices is reduced to make electronic devices smaller, then the device size decreases, but the bit error rate increases
Solution Approach 1:
The patent applies local quality by implementing error correction code (ECC) operations specifically on sub-pages rather than entire pages, and by performing targeted refresh operations on memory cell rows with high error occurrence counts. This localized approach addresses bit errors in specific problematic areas without requiring full-page processing, thereby maintaining reliability in smaller devices while avoiding excessive overhead.
Solution Approach 2:
The patent segments the memory page into sub-pages for ECC operations, allowing error correction to be performed on smaller, manageable units. This segmentation enables more efficient error handling in compact devices where full-page ECC would consume excessive resources, thus addressing the reliability issue in reduced-size DRAM devices.
2Reliability
If robust ECC operation is implemented to correct bit errors, then data integrity is improved, but the device complexity increases
Solution Approach 1:
The patent implements ECC operations on sub-pages rather than entire pages, reducing the complexity of ECC processing. By focusing ECC resources on smaller sub-page units and combining this with targeted refresh operations on error-prone rows, the system achieves robust error correction with reduced computational overhead and simpler implementation.
Solution Approach 2:
The patent performs ECC operations on partial pages (sub-pages) rather than complete pages, and performs refresh operations only on memory rows with high error counts rather than all rows. This partial action approach provides sufficient error correction capability to maintain data integrity while significantly reducing the complexity compared to full-page ECC and universal refresh.
3Duration of action of stationary object
If the number of refresh operations is increased in error-prone memory rows, then data retention is improved, but the energy consumption increases
Solution Approach 1:
The patent applies refresh operations selectively to memory cell rows with high error occurrence counts identified through ECC decoding, rather than uniformly refreshing all memory rows. This localized refresh approach extends data retention in error-prone areas while minimizing energy consumption by avoiding unnecessary refresh operations in reliable memory regions.
Solution Approach 2:
The patent uses feedback from ECC decoding operations to identify memory rows with high error occurrence counts, then uses this information to adjust refresh operations dynamically. This feedback mechanism ensures data retention is improved in problematic rows while energy is conserved by not over-refreshing reliable rows, achieving optimal balance between retention and power consumption.
Data Source
AI summary
The present disclosure relates to a semiconductor memory device. The semiconductor memory device includes memory cell array, error correction code (ECC) engine, refresh control circuit and control logic circuit. The memory cell array includes memory cell rows. The refresh control circuit performs a refresh operation on the memory cell rows. The control logic circuit controls the ECC engine such that the ECC engine generates an error generation signal by performing ECC decoding on sub-pages in at least one first memory cell row during a read operation. The control logic circuit compares an error occurrence count of the first memory cell row with a threshold value and provides the refresh control circuit with a first address of the first memory cell row as an error address based on the comparison. The refresh control circuit increases a number of refresh operations performed in the first memory cell row during a refresh period.