ECC Generator Buffering to Cut DRAM Row Switching Delays
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Solution Overview
Problem
Conventional error correction code generators face inefficiencies due to frequent row address switching in dynamic random access memory (DRAM), leading to increased encoding time and reduced access efficiency when generating error correction codes like Reed-Solomon product codes.
Innovation Solution
The implementation of an additional static random access memory (SRAM) and a multi-symbol encoder to reduce the number of row address switches during data access, by pre-loading and processing multiple data columns from DRAM into SRAM for faster encoding operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional DRAM is used to store and access source data for error correction code generation, then data storage capacity is sufficient, but encoding efficiency decreases due to frequent row address switching and charge time delays
Solution Approach 1:
The patent applies preliminary action by pre-loading multiple columns of source data into the DRAM before encoding operations begin. This allows the encoder to access consecutive columns without triggering row address switches, as all required data is already loaded into the same memory page. The pre-loading phase prepares the data in advance, eliminating wait times during the actual encoding process.
Solution Approach 2:
The patent introduces an intermediary buffer memory structure between the DRAM and the encoder. This buffer holds multiple columns of data and manages the data flow to the encoder, allowing the encoder to continuously access data without causing row address switches in the DRAM. The intermediary buffer absorbs the mismatch between DRAM access patterns and encoder requirements.
2Ease of operation
If row address switching is performed frequently to access different data columns in DRAM, then complete data access is enabled, but access efficiency deteriorates due to charge time requirements
Solution Approach 1:
The system performs preliminary action by loading all required columns into the DRAM before the encoding process starts. This pre-loading ensures that when the encoder needs to access different columns, the data is already in the memory page, eliminating the need for row address switches and associated charge times during encoding.
Solution Approach 2:
The patent enables continuous data access by organizing the data loading and encoding process to maintain the memory page open throughout the encoding operation. Once the first column is loaded into a memory page, subsequent columns are accessed within the same page without closing and reopening, thus maintaining continuous useful action without charge time interruptions.
3Reliability
If multiple PO columns are accessed sequentially from DRAM during encoding, then encoding completeness is achieved, but the number of row address switches increases
Solution Approach 1:
The patent applies preliminary action by loading all necessary PO columns into the DRAM before the encoding process begins. This pre-loading phase ensures that when the encoder sequentially accesses multiple PO columns, all data is already available in the memory page, eliminating the need for row address switches and reducing the complexity of address management.
Solution Approach 2:
The patent merges multiple column access operations into a single continuous process by loading all required columns into the same memory page beforehand. This combining of data into a unified memory space allows the encoder to sequentially access all PO columns without triggering row address switches, simplifying the address switching operations.
Data Source
AI summary
An error correction code generator uses an additional static random access memory (SRAM) or a multi-symbol encoder to improve the encoding efficiency. During the encoding operation, the number of the data access of the dynamic random access memory (DRAM) with the row address switching can be reduced considerably via using the additional SRAM or multi-symbol encoder. Hence, the efficiency of the data access of the DRAM is improved and the encoding time of the error correction code generator is reduced.