ECC Checker Circuit for High-Speed Data Error Detection
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Solution Overview
Problem
Existing error correcting codes (ECCs) struggle to efficiently detect and correct data corruption at high data rates exceeding the processing capabilities of linear feedback shift registers, requiring new circuits that reduce logic complexity and enhance error detection capabilities.
Innovation Solution
A circuit using an ECC checker, memory arrangement, and detection circuit that generates an error indication by processing portions of the remainder from an ECC check, allowing for efficient detection and optional correction of data corruption, including single-bit errors, using a reduced look-up table and dual port memory or parallel memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If linear feedback shift registers are used for ECC check, then error detection and correction capability is achieved, but processing rate is insufficient for high-speed serial data communication
Solution Approach 1:
The patent divides the remainder from the ECC check into multiple portions (first portion and second portion) and processes them separately through different memory arrangements, enabling parallel processing that increases the processing rate while maintaining error detection capability
Solution Approach 2:
The patent transitions from sequential processing in linear feedback shift registers to a parallel processing architecture using multiple memory arrangements (dual port memory or parallel memories) that operate simultaneously on different portions of the remainder, thereby achieving high-speed processing
2Productivity
If traditional ECC check circuits are used, then error detection is performed, but logic complexity is high and processing speed is limited
Solution Approach 1:
The patent extracts only the necessary portions of the remainder (first portion and second portion) for error detection and processes them through simplified memory arrangements, removing unnecessary logic complexity while maintaining processing speed
Solution Approach 2:
The patent uses memory arrangements that store pre-computed values corresponding to different error conditions, allowing rapid lookup and comparison without complex real-time computation, thereby reducing logic complexity while enabling high-speed operation
Data Source
AI summary
A circuit and method efficiently provide detection of corruption of data using an error correcting code (ECC). The circuit includes an ECC checker, a memory arrangement, and a detection circuit. The ECC checker generates a remainder of an ECC check of the data and an ECC value generated from an uncorrupted version of the data. The memory stores a set of values and receives a first portion of the remainder at a first address port and a second portion of the remainder at a second address port. The memory arrangement outputs a first value of the set responsive to a value of the first portion and output a second value of the set responsive to a value of the second portion. The detection circuit generates an error indication in response to the first and second values to indicate whether a single bit of the data is incorrect.