Other Decoding Techniques TRIZ Cases
- Adaptive Parity Check Matrix for Iterative Block Code Decoding
Bit-reliability-guided matrix sparsification improves iterative block code decoding, reducing error propagation and check saturation.
- Wireless Receiver Decoding with Alternative Path Integrity Checks
Alternative path decoding and integrity checks help wireless receivers recover correct data under channel impairments with lower resource use.
- Serially Concatenated Turbo Decoding With Overlapped Decoder Processing
Shuffled decoding overlaps internal and external processing to reduce turbo-decoder latency.
- Secure Seed Deterministic Function for Distributed Storage Security
Incorporating a secure seed into the deterministic function prevents malicious agents from predicting data storage locations and degrading system performance.
- Memory Controller Read Disturbance Mitigation via Verification Reads
A memory controller performs reliability verification reads on unselected word lines to detect data errors.
- Parallelized Successive Cancellation Decoding for Polar Codes
Segmenting the decoding tree into parallel units reduces latency while maintaining computational complexity.
- LDPC Decoder Parallel SISO Architecture Single Memory Cycle
Segmented memory arrays enable single cycle iterations, reducing memory bit requirements while maintaining decoding accuracy.
- ECC Checker Circuit for High-Speed Data Error Detection
A circuit uses an ECC checker and memory arrangement to generate error indications from remainder portions.
- Minimum Euclidean Distance Finder for MIMO Symbol Detection
A modem chip calculates minimum Euclidean distances using index-based comparators to reduce hardware size.
- Parallel Bit Error Detection Using Time Signatures
A parallel bit error detection system processes data packet bits independently using a time signature to generate immediate error flags.