Serially Concatenated Turbo Decoding With Overlapped Decoder Processing

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Solution Overview

Problem

Existing serially concatenated convolutional turbo decoders suffer from high decoding latency due to the sequential dependency between internal and external decoders, which limits throughput and efficiency.

Innovation Solution

Implement a 'shuffled' decoding technique that allows the external decoder to start decoding independently of the internal decoder, utilizing a parallel processing architecture to overlap decoding steps and reduce waiting times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sequential decoding is used between internal and external decoders, then decoding accuracy is maintained, but decoding latency increases and throughput decreases

Engineering Contradiction:

Improvedecoding accuracyVSAvoiddecoding latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The external decoder performs preliminary decoding actions before the internal decoder completes its processing. By allowing the external decoder to start decoding early using initially available data, the system overlaps decoding operations and reduces total latency while maintaining accuracy through subsequent refinement iterations

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The decoding process maintains continuous useful action by eliminating idle waiting periods. The external decoder remains active and productive throughout the decoding process, continuously processing data and generating extrinsic information rather than waiting for the internal decoder to complete, thus improving throughput without sacrificing accuracy

Inventive Principle:

Principle #20Continuity of useful action

2Productivity

If parallel processing architecture is implemented to reduce decoding latency, then throughput increases, but hardware resource requirements increase proportionally

Engineering Contradiction:

ImprovethroughputVSAvoidhardware resources

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The system dynamically adjusts the degree of parallelism and resource allocation based on decoding stage and data availability. Rather than implementing fixed full parallelism, the architecture dynamically enables external decoder operations when data is ready, optimizing the balance between throughput improvement and hardware resource utilization

Inventive Principle:

Principle #15Dynamics

Data Source

PatentEP4335034B1Decoding of serially concatenated turbo codes

Publication Date: 2025.07.23 ZODIAC DATA SYSTEMS

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AI summary

Series turbo-decoder, series turbo-decoding method and computer program product, the series turbo-decoder comprises an input configured to receive a word to be decoded comprising informative data or payload data, internal and external redundancy data, an internal decoder (DCI) and an external decoder (DCE). The internal decoder and the external decoder receive the word simultaneously. The internal decoder is configured to perform part of the decoding of the word based on the payload data and on the internal and external redundancy data. The external decoder is configured to perform another part of the decoding of the word based on the payload data and on the external redundancy data without awaiting the availability of information extrinsic to the internal decoder.