LDPC Decoder Parallel SISO Architecture Single Memory Cycle
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Solution Overview
Problem
Current LDPC error correction systems face inefficiencies in memory usage and processing speed due to the need for multiple memory cycles and high-resolution memory, particularly in handling permutations and storing data during iterative decoding processes.
Innovation Solution
A parallel SISO decoder structure that updates Log-likelihood-ratios in a single operation, utilizing a difference array and a current array with low-resolution memory for efficient memory management, and representing differences in permuted form to reduce the number of permutations required, allowing for single memory cycle iterations with reduced memory bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fast LDPC architecture is used with single memory cycle iterations, then processing speed is improved, but memory resolution requirements increase to high-resolution
Solution Approach 1:
The patent segments the memory system into two distinct parts: a difference array memory storing low-resolution data (d_i,k values) and a current array memory storing high-resolution data (c_k values). This segmentation allows the fast architecture to operate with reduced overall memory resolution requirements, as only the current array needs high resolution while the difference array uses low resolution, resolving the contradiction between speed and memory resolution requirements.
Solution Approach 2:
The patent applies local quality by assigning different resolution characteristics to different memory locations based on their functional requirements. The difference array uses low-resolution storage sufficient for storing incremental updates, while the current array maintains high-resolution storage for the actual codeword values. This localized quality assignment optimizes the overall system by avoiding unnecessary high-resolution storage throughout, thus reducing memory bit requirements while maintaining processing speed.
2Measurement precision
If a slow LDPC architecture is used with two cycles per iteration, then memory resolution requirements are reduced, but processing speed decreases
Solution Approach 1:
The patent implements dynamic operation by enabling the memory system to switch between different operational modes. The architecture supports single memory cycle iterations with dynamic data routing and permutation handling, allowing the system to achieve fast processing speeds while maintaining efficient memory usage. This dynamic capability eliminates the need for the slow two-cycle architecture while preserving memory efficiency through proper management of the difference and current arrays.
3Reliability
If multiple permutations are handled in LDPC decoding, then decoding accuracy is improved, but the number of memory locations and processing complexity increase
Solution Approach 1:
The patent applies discarding and recovering by temporarily storing permutation information in the difference array during processing, then recovering and applying the correct permutations to update the current array. This approach allows multiple permutations to be handled accurately without requiring separate high-resolution storage for each permutation variant, thus maintaining decoding accuracy while reducing overall memory complexity and location requirements.
Data Source
AI summary
The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratios in a single operation, as opposed to the two pass traditionally associated with the Tanner Graphs. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISOs. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.