Semiconductor Memory ECC and DBI Circuit Parallel Operation
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Solution Overview
Problem
In semiconductor memory apparatuses that perform both error check and data bus inversion functions, the latency in read operations is increased due to the sequential execution of these functions, which impedes data processing speed.
Innovation Solution
The error check and correction circuit block and the data bus inversion circuit block operate simultaneously, with the DBI circuit block performing data inversion based on error data discrimination signals and logic levels, allowing both error-checked and inverted data to be outputted concurrently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error check and data bus inversion functions are performed sequentially, then each function can be completed accurately, but the latency in read operations increases and data processing speed decreases
Solution Approach 1:
The patent applies preliminary action by performing the data bus inversion operation concurrently with the error check operation rather than sequentially. The DBI circuit block receives cell data and generates inverted data in parallel with the ECC circuit block performing error checking, so that both operations complete simultaneously rather than one waiting for the other, thereby reducing read operation latency while maintaining accuracy of both functions
Solution Approach 2:
The patent merges the error check function and data bus inversion function into a concurrent execution model. Both the ECC circuit block and DBI circuit block operate simultaneously on the same cell data, combining what were previously sequential operations into parallel processes that share the same time window, thus eliminating the additional latency that would result from sequential execution
2Reliability
If error check and data bus inversion functions are performed sequentially, then functional correctness is maintained, but data processing speed is impeded
Solution Approach 1:
The patent applies preliminary action by initiating the data bus inversion operation at the same time as the error check operation begins, rather than waiting for error checking to complete first. This allows the DBI circuit block to process cell data and generate inverted data concurrently with the ECC circuit block, thereby accelerating data processing speed while ensuring both functions complete correctly
Solution Approach 2:
The patent merges two previously sequential processing stages (error check and data bus inversion) into a single concurrent processing window. Both circuit blocks operate in parallel on the same input data, effectively combining what were two separate time-consuming operations into one simultaneous operation, thus improving overall data processing speed without sacrificing correctness
Data Source
AI summary
A semiconductor memory apparatus may include an error check and correction circuit block configured to receive a plurality of cell data, and output error-checked data and error data discrimination signals after receiving an error check enable signal; and a data bus inversion circuit block configured to receive the plurality of cell data, and output the plurality of cell data by inverting or non-inverting the cell data after receiving a read data bus inversion enable signal, the error check enable signal and the error data discrimination signals.