Run-time ECC Error Injection for Hardware Validation

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Solution Overview

Problem

Microcontroller devices with Error Correcting Code (ECC) features face challenges in runtime checking and fault injection for safety critical systems, particularly in handling simultaneous faults, which requires a method to test fault logic effectively and ensure functional safety.

Innovation Solution

A run-time ECC error injection scheme is implemented, allowing for the configuration of read and write paths to internally forward data and inject faulty bits under program control, using read and write fault injection logic to simulate errors in ECC modules, enabling comprehensive and fast functional testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If runtime fault injection is implemented for safety critical systems, then functional safety testing capability is improved, but device complexity increases

Engineering Contradiction:
Improvefunctional safety testing capabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The fault injection logic is nested within the existing ECC module structure, with read fault injection logic and write fault injection logic integrated into the respective data paths. This allows fault injection functionality to be embedded without adding separate external testing hardware, thus improving safety testing capability while minimizing additional device complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The ECC module is designed to serve dual purposes: normal error correction operations and fault injection for safety testing. The same ECC infrastructure handles both legitimate error correction and intentional fault injection, allowing one component to perform multiple functions and reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If fault injection logic is added to simulate errors, then testing capability for simultaneous faults is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvetesting capability for simultaneous faultsVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The fault injection capability is segmented into independent read fault injection logic and write fault injection logic, each handling specific fault injection scenarios. This segmentation allows the system to test for simultaneous faults by independently controlling read and write path fault injection, improving testing versatility while keeping each segment's manufacturing complexity manageable.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If internal forwarding of read and write data is implemented, then fault injection accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvefault injection accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Internal forwarding paths act as intermediaries between the fault injection logic and the actual data storage/retrieval operations. The read data is internally forwarded through the fault injection logic before reaching the output, and write data is forwarded through the fault injection logic before storage. This intermediary approach ensures accurate fault injection while utilizing existing data paths to minimize additional complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10248521B2Run time ECC error injection scheme for hardware validation
Publication Date: 2019.04.02 MICROCHIP TECHNOLOGY INC
  • US10248521B2 patent drawing
  • US10248521B2 patent drawing
  • US10248521B2 patent drawing

AI summary

Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.