On-Chip ECC Memory Device Parallel Cell Testing
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Solution Overview
Problem
The implementation of an on-chip ECC scheme in memory devices increases test time due to the need to write and read test data in both normal and parity cell regions, making efficient testing of these regions challenging.
Innovation Solution
A method is introduced that includes parity generation circuits, test input circuits, write circuits, and test output circuits to generate and compare parity bits, allowing for simultaneous testing of normal and parity cell regions, thereby reducing test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits for ECC are allocated and stored in specific memory regions (parity cell regions) of the memory array, then data error correction capability is improved, but test time increases due to the need to write and read test data in both normal and parity cell regions
Solution Approach 1:
The patent merges the testing of normal cell regions and parity cell regions into a single unified test operation. By generating individual test bits from the comparison between write data and common test bits, and writing these individual test bits to parity cell regions while writing write data to normal cell regions, the system tests both regions simultaneously in one write-read cycle, thereby reducing overall test time while maintaining comprehensive test coverage
Solution Approach 2:
The patent performs preliminary generation of common test bits and individual test bits before the actual write operation to memory cells. The common input circuit generates common test bits by comparing parity bits from multiple banks, and the individual input circuit generates individual test bits by comparing write data with common test bits. This preliminary preparation enables the subsequent write operation to test both normal and parity regions efficiently without requiring separate test sequences
2Productivity
If a parallel-bit test (PBT) is performed by writing specific test data to all memory cells and comparing output data, then throughput is improved, but test completeness deteriorates when ECC parity cells are involved due to additional testing requirements
Solution Approach 1:
The patent makes the test data generation and write operation universal by creating a system that simultaneously handles both normal cell testing and parity cell testing through a single mechanism. The common input circuit and individual input circuit work together to generate appropriate test bits for both region types, and the write circuit writes both write data and individual test bits in one operation, ensuring that one test sequence comprehensively validates both normal and ECC parity regions without requiring separate specialized test procedures
Data Source
AI summary
A memory device adopting an on-chip ECC scheme includes a plurality of banks, each including a normal cell region and a parity cell region; a plurality of parity generation circuits, each generating parity bits for write data to be stored in the normal cell region within a corresponding bank; a test input circuit generating common test bits by comparing the parity bits of the respective banks, and generating individual test bits by comparing bits of the write data with the common test bits; a plurality of write circuits, each writing the write data to the normal cell region within the corresponding bank and writing the individual test bits to the parity cell region within the corresponding bank; and a plurality of test output circuits, each comparing data read from the normal region with the individual test bits read from the parity cell region within a corresponding bank.