ECC Circuit Error Correction for Semiconductor Memory

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Solution Overview

Problem

The increasing reduction in fabrication design rules of DRAM devices leads to higher bit errors in memory cells, reducing the yield of error-free memory cells and affecting the reliability of semiconductor memory devices.

Innovation Solution

An error correction circuit is implemented in semiconductor memory devices, utilizing an error correction code (ECC) represented by a generation matrix to generate parity data and correct error bits in main data, with the ECC dividing data bits into sub units to gather mis-corrected and multiple error bits in one symbol, enabling correction of multiple error bits when they cannot be detected individually.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If fabrication design rules are reduced to increase memory density, then storage capacity is improved, but bit error rate increases

Engineering Contradiction:

Improvememory densityVSAvoidbit error rate

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The main data is divided into multiple sub data units, and the ECC is structured with column vectors divided into code groups corresponding to these sub units. This segmentation allows the error correction circuit to process and identify error patterns more effectively, gathering mis-corrected bits and multiple error bits into one symbol for correction.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An error correction circuit with an enhanced ECC engine is introduced as an intermediary between the memory cell array and the data output. This intermediary processes the main data through parity generation and error detection/correction mechanisms, eliminating error bits before data is returned to the user, thus resolving the reliability issue caused by reduced fabrication rules.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If conventional ECC is used to correct error bits, then error correction capability is provided, but multiple error bits and mis-corrected bits cannot be gathered for correction

Engineering Contradiction:

Improveerror correction capabilityVSAvoiduncorrected error bits

Core Design Contradiction:

ReliabilityVSLoss of information

Solution Approach 1:

The ECC is divided into multiple code groups corresponding to sub data units, with column vectors structured to enable gathering of error bits. This segmentation allows the syndrome generation circuit to identify and gather mis-corrected bits and multiple error bits into one symbol, enabling comprehensive error correction that conventional ECC cannot achieve.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11436079B2Semiconductor memory devices having enhanced error correction circuits therein

Publication Date: 2022.09.06 SAMSUNG ELECTRONICS CO LTD

AI summary

An error correction circuit includes an error correction code (ECC) memory and an ECC engine. The ECC memory stores an ECC, which is at least partially represented by a generation matrix. The ECC engine generates parity data based on main data using the ECC, and detects and/or corrects at least one error bit in the main data read from the memory cell array using the parity data. The main data includes a plurality of data bits divided into a plurality of sub data units. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub data units. The column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol and the mis-corrected bit is generated due to the multiple error bits in the main data.