ECC-Guided Memory Cell Reset for Read Disturb Under PVT
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Solution Overview
Problem
Memory cells, particularly under process voltage temperature (PVT) conditions, suffer from read disturb effects that lead to data loss and failed read operations due to increased read voltage levels and operation temperatures, causing incorrect data retrieval.
Innovation Solution
A semiconductor device configuration that includes a memory circuit, error correction code circuit, logic circuit, and write circuit, which detects read disturb errors, generates error information, and resets memory cells using pulse signals with lower voltage levels and shorter durations to prevent damage and correct data, thereby maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If higher read voltage levels are used to improve read operation speed, then read speed is improved, but read disturb effect increases causing data loss
Solution Approach 1:
The patent implements dynamic read voltage adjustment based on detected read disturb effects. The read voltage level is adaptively modified according to the magnitude of read disturb detected during operation, allowing the system to maintain high read speeds when conditions permit while reducing voltage to prevent data loss when read disturb becomes problematic.
Solution Approach 2:
The patent changes the read voltage parameter dynamically based on operating conditions and detected read disturb effects. By monitoring read disturb magnitude and adjusting the voltage level accordingly, the system optimizes the trade-off between read speed and data integrity, preventing data loss while maintaining efficient operation.
2Productivity
If higher operation temperatures are used to improve device performance, then device performance is improved, but read disturb effect increases causing failed read operations
Solution Approach 1:
The patent implements a feedback mechanism that monitors read disturb effects during operation and uses this information to adjust subsequent read operations. When increased temperature causes elevated read disturb, the system detects this through monitoring mechanisms and adjusts read strategies or applies compensatory measures to maintain reliable read operations despite thermal conditions.
Solution Approach 2:
The patent dynamically adjusts read operation parameters in response to temperature-induced read disturb effects. The system adapts its behavior based on real-time detection of read disturb magnitude, allowing it to maintain high device performance while compensating for temperature-related reliability degradation through adaptive control.
3Reliability
If read voltage levels are reduced to prevent read disturb effects, then data integrity is improved, but read operation speed decreases
Solution Approach 1:
The patent implements dynamic read voltage adjustment based on detected read disturb effects. The read voltage level is adaptively modified according to the magnitude of read disturb detected during operation, allowing the system to maintain high read speeds when conditions permit while reducing voltage to prevent data loss when read disturb becomes problematic.
Solution Approach 2:
The patent changes the read voltage parameter dynamically based on operating conditions and detected read disturb effects. By monitoring read disturb magnitude and adjusting the voltage level accordingly, the system optimizes the trade-off between read speed and data integrity, preventing data loss while maintaining efficient operation.
4Reliability
If memory cells are reset frequently to correct read disturb errors, then data accuracy is improved, but operational efficiency decreases due to additional reset operations
Solution Approach 1:
The patent implements a feedback mechanism that monitors read disturb effects during operation and uses this information to adjust subsequent read operations. When increased temperature causes elevated read disturb, the system detects this through monitoring mechanisms and adjusts read strategies or applies compensatory measures to maintain reliable read operations despite thermal conditions.
Solution Approach 2:
The patent applies reset operations selectively rather than continuously, using partial action principle. Reset operations are triggered only when read disturb effects exceed certain thresholds or when specific error patterns are detected, rather than applying resets to all memory cells regardless of condition. This approach maintains data accuracy for affected cells while minimizing the overall impact on operational efficiency.
Data Source
AI summary
A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.