On-Chip ECC Circuit Segmentation for Parity Storage Optimization
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Solution Overview
Problem
Conventional on-chip ECC circuits in memory devices perform only memory-side ECC operations, leading to increased parity storage requirements, which reduces the area and capacity for data storage.
Innovation Solution
Incorporating an on-chip ECC circuit that performs both host-side and memory-side ECC operations, allowing for the separation of host parity and memory parity storage, thereby minimizing parity storage space and optimizing data storage area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If only memory-side ECC operation is performed in conventional on-chip ECC circuits, then the ECC function is simplified, but parity storage requirements increase, reducing data storage area
Solution Approach 1:
The ECC operation is segmented into two independent parts: host-side ECC operation and memory-side ECC operation. The host-side ECC circuit processes host parity separately from the memory-side ECC circuit that processes memory parity. This segmentation allows each circuit to handle only its specific parity type, reducing the total parity storage requirements in the memory device while maintaining comprehensive error correction capabilities.
2Reliability
If host parity is stored in the memory device, then complete ECC operation can be performed, but parity storage space increases, reducing data storage capacity
Solution Approach 1:
The host parity processing function is extracted from the memory device and placed in a separate host-side ECC circuit. The memory device now only needs to store and process memory parity, which is generated solely from the data stored in the memory device. This extraction eliminates the need to store host parity in the memory device, thereby increasing data storage capacity while maintaining complete ECC operation through the separate host-side circuit.
3Measurement precision
If on-chip ECC circuit performs both host-side and memory-side ECC operations, then data communication precision is improved, but device complexity increases
Solution Approach 1:
The on-chip logic block is designed with multi-functionality, incorporating both host-side ECC circuit and memory-side ECC circuit within a single integrated structure. This universal design allows the same physical block to perform multiple ECC operations (host-side and memory-side) using different parity types, thereby improving data communication precision without requiring separate discrete circuits for each ECC function.
Data Source
AI summary
An on-chip logic block may include a host ECC circuit configured to correct an error based on host parity. The on-chip logic block may include a memory ECC circuit configured to correct an error based on memory parity.