ECC Redundancy Memory for Low-Power Reliable SRAM Repair
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Solution Overview
Problem
Conventional memory redundancy systems, such as CAM redundancy circuits, consume excessive power and suffer from reliability issues due to parallel checking and soft errors, particularly in SRAM-based systems, which can lead to incorrect redundancy implementations and error accumulation over time.
Innovation Solution
Implementing an integrated circuit with a data array and a separate SRAM redundancy memory that uses error correction codes (ECC) for verification and correction, where each data memory segment has a corresponding redundancy word containing information about bad rows and columns, allowing for efficient error detection and correction, thereby reducing power consumption and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CAM redundancy schemes with parallel checking are used, then memory reliability is improved, but power consumption increases significantly
Solution Approach 1:
The patent divides the memory system into separate data memory segments and corresponding redundancy memory segments. Each redundancy word is specifically assigned to protect a particular data memory segment, enabling targeted error correction without requiring parallel checking across the entire memory array. This segmentation allows the system to achieve reliability through localized redundancy while reducing overall power consumption.
Solution Approach 2:
The patent implements periodic error checking of redundancy words at predetermined intervals rather than continuous parallel checking. The error correction circuit periodically verifies the integrity of redundancy words and corrects errors when detected, which significantly reduces power consumption compared to continuous checking while maintaining memory reliability through regular validation.
2Reliability
If parallel checking is implemented in CAM redundancy schemes, then error detection capability is improved, but memory access efficiency deteriorates
Solution Approach 1:
The patent performs preliminary error checking and correction of redundancy words at predetermined intervals before they are needed for actual memory operations. By proactively maintaining the integrity of redundancy words through periodic verification, the system ensures error detection capability is ready when needed without interfering with normal memory access operations, thus preserving memory access efficiency.
Solution Approach 2:
The error correction circuit automatically detects and corrects errors in redundancy words without requiring external intervention or parallel checking operations. The system self-services by periodically validating its own redundancy structures, ensuring error detection capability is maintained independently of normal memory access operations, thereby avoiding efficiency deterioration.
3Use of energy by moving object
If redundancy words are not periodically verified, then power consumption is reduced, but error accumulation occurs over time
Solution Approach 1:
The patent implements periodic verification of redundancy words at predetermined intervals to detect and correct errors before they accumulate. This periodic action strikes an optimal balance between power consumption and reliability by performing error checking only when necessary, rather than continuously, thus preventing error accumulation while minimizing power usage.
Solution Approach 2:
The error correction circuit provides feedback by monitoring the integrity of redundancy words and triggering correction operations when errors are detected. This feedback mechanism ensures that errors are caught and corrected periodically, preventing accumulation over time, while the feedback-driven approach allows the system to remain in a low-power state between verification cycles.
Data Source
AI summary
An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.