Memory ECC Sub-Channel Isolation for RAS Overhead Reduction
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Solution Overview
Problem
The increasing overhead for error handling in memory channels, particularly with narrower channels, makes it challenging to maintain reliability, availability, and scalability (RAS) while meeting SDDC expectations, as the RAS overhead increases significantly with newer memory systems.
Innovation Solution
The implementation of ECC sub-channel isolation within memory devices, where the N-bit channel is treated as two N/2-bit sub-channels for internal ECC, allowing for separate correction of each sub-channel, reducing the overall ECC overhead and enabling more efficient error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC bits are used for SDDC operation in narrower channels, then reliability is improved, but RAS overhead increases significantly
Solution Approach 1:
The patent divides the N-bit channel into two separate N/2-bit sub-channels for internal ECC processing. This segmentation allows the ECC to be applied to smaller data portions independently, reducing the overall ECC overhead while maintaining the ability to correct errors in the full channel. The internal ECC circuitry processes each sub-channel separately and then combines the results for system-level ECC.
2Reliability
If full channel ECC is applied, then error correction capability is maintained, but ECC overhead increases with narrower channels
Solution Approach 1:
The patent segments the channel into two N/2-bit sub-channels and applies ECC to each sub-channel separately. This approach reduces the ECC overhead by half compared to applying full channel ECC to the entire N-bit channel, while still providing comprehensive error correction coverage through the combined sub-channel corrections.
Solution Approach 2:
The patent applies partial ECC to sub-channels rather than full ECC to the entire channel. By treating the N-bit channel as two separate N/2-bit sub-channels and applying ECC to each portion independently, the system achieves sufficient error correction capability with reduced overhead, accepting that some error correction functionality may be redundant but eliminating excessive overhead.
3Adaptability or versatility
If narrower channels are used, then scalability is improved, but RAS overhead increases
Solution Approach 1:
The patent implements segmentation of the channel into sub-channels that can be processed independently by internal ECC circuitry. This allows narrower channels to maintain lower RAS overhead by processing errors in smaller data portions separately, making the system more adaptable to different channel widths while controlling overhead.
Solution Approach 2:
The patent creates a dynamic ECC processing approach where the channel can be flexibly divided into sub-channels based on the specific channel width and error correction requirements. This dynamic segmentation allows the system to adapt to different channel configurations (e.g., 32-bit vs. 64-bit channels) and adjust the ECC overhead accordingly, maintaining scalability.
Data Source
AI summary
A memory device that performs internal ECC (error checking and correction) can treat an N-bit channel as two N/2-bit channels for application of ECC. The memory device includes a memory array to store data and prefetches data bits and error checking and correction (ECC) bits from the memory array for a memory access operation. The memory device includes internal ECC hardware to apply ECC, with a first group of a first half the data bits checked by a first half of the ECC bits in parallel with a second group of a second half of the data bits checked by a second half of the ECC bits.