ECC Circuit Syndrome Bit Segmentation for Paired Bit Error Correction
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Solution Overview
Problem
Conventional error correction codes in semiconductor memory devices fail to effectively correct errors when multiple memory cells fail, particularly when failures occur in adjacent cells along a word line, due to limitations in generating syndrome bits for single and paired data bit errors.
Innovation Solution
The proposed solution involves an error correction code (ECC) circuit that generates syndrome bits for both individual data bits and selected pairs of data bits, leveraging an existing logic tree structure without increasing the circuit size, by assigning specific syndrome values to correct single and paired bit errors, and using a matrix to manage these values efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction codes are used to correct single bit errors, then single bit error correction is achieved, but multiple bit errors (particularly adjacent pairs) cannot be corrected
Solution Approach 1:
The syndrome bits are segmented into two distinct groups: one group identifies single bit errors while another group identifies paired bit errors. This segmentation allows the ECC circuit to independently handle different error patterns using dedicated syndrome bit sets, thereby achieving both single bit and paired bit error correction capabilities without interference between the two functions.
Solution Approach 2:
The ECC circuit is designed with multi-functionality to handle both single bit errors and paired bit errors using the same basic circuit structure. By assigning different syndrome bit values to represent different error types, the circuit achieves universal error correction capability for multiple error patterns without requiring separate dedicated circuits for each error type.
2Reliability
If additional syndrome bits are generated to correct paired bit errors, then paired bit error correction capability is improved, but circuit complexity and size increase
Solution Approach 1:
The syndrome generation circuits for single bit errors and paired bit errors are merged into a unified ECC circuit structure. The same logic tree and syndrome generation resources are used to produce both single-bit syndromes and paired-bit syndromes by simply interpreting different syndrome bit values differently, thereby avoiding duplication of circuit resources and maintaining compact circuit size.
Solution Approach 2:
The ECC circuit achieves multi-functionality by using the existing syndrome generation infrastructure to serve dual purposes: generating syndromes for single bit errors and syndromes for paired bit errors. This is accomplished through intelligent assignment of syndrome values rather than through additional hardware, thus improving paired bit error correction without proportionally increasing circuit complexity.
3Measurement precision
If more syndrome values are assigned to cover both single and paired bit errors, then error detection accuracy is improved, but the mapping complexity between syndrome values and error locations increases
Solution Approach 1:
Different portions of the syndrome bit space are assigned different functions: certain syndrome values are dedicated to identifying single bit errors while other syndrome values are dedicated to identifying paired bit errors. This local quality assignment allows the system to maintain simple, dedicated mapping rules for each error type rather than requiring a single complex mapping rule that handles all error patterns uniformly.
Data Source
AI summary
Apparatuses, systems, and methods for error correction for selected bit pairs. A memory device may include an error correction code (ECC) circuit which may receive data bits as part of a read or write operation and generate parity bits based on the data bits. The parity bits may be used to locate and correct errors in the data bits. The parity bits may be generated based on a syndrome value. Each of the individual data bits may be associated with a syndrome value. In addition, some selected pairs of data bits may also be associated. with a syndrome value. This may allow the ECC circuit to correct errors in individual data bits or in one of the selected pairs of data bits. In some embodiments, the selected pairs may represent adjacent memory cells along a word line.