ECU Access Violation Timing for Accurate Task Identification
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Solution Overview
Problem
Existing microcomputers face inefficiencies in detecting and identifying tasks causing access privilege violations due to discrepancies in processing speeds between the CPU and input/output devices, leading to delays and errors in determining the responsible task, especially when interrupts are prohibited during task switching.
Innovation Solution
An electronic control unit with a time storage mechanism that records the detection time of access violations and compares it with task switching times to accurately identify the task causing the violation, using non-maskable interrupts even during interrupt prohibition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the CPU waits for the completion of access to the low-speed control register, then data accuracy is ensured, but processing efficiency deteriorates
Solution Approach 1:
The patent introduces a buffer memory that pre-stores data before it is needed by the CPU. The input/output device writes data to the buffer in advance, and the CPU retrieves it asynchronously, eliminating the need for the CPU to wait for low-speed device completion while ensuring data accuracy is maintained through the buffer's staged transfer mechanism.
Solution Approach 2:
The buffer memory acts as an intermediary between the CPU and the input/output device. It mediates the speed mismatch by receiving data from the slow device and providing it to the fast CPU on demand, allowing both components to operate at their respective optimal speeds without direct synchronization requirements.
2Reliability
If the access violation detection mechanism monitors all memory areas including control registers, then security is improved, but the number of monitorable areas exceeds the CPU's capacity
Solution Approach 1:
The patent segments the memory monitoring function by introducing a dedicated access violation detection mechanism that operates independently from the main CPU monitoring capacity. This separate detection mechanism specifically monitors control register areas that would otherwise exceed the CPU's monitorable area limit, allowing comprehensive security coverage without overwhelming the CPU's existing monitoring capabilities.
3Stability of the object's composition
If interrupts are prohibited during task switching to maintain consistency, then system consistency is improved, but the delay in detecting and identifying access violations increases
Solution Approach 1:
The access violation detection mechanism records the timing information of violations in advance, storing them in a buffer or memory structure. When the interrupt prohibition is lifted and task switching completes, the system can immediately retrieve and process these pre-recorded violation records without delay, thus maintaining system consistency during task switching while minimizing detection and identification time afterward.
4Productivity
If the input/output device detects access violations asynchronously via buffer, then processing efficiency is improved, but the timing of violation detection diverges from CPU execution timing
Solution Approach 1:
The buffer serves as an intermediary that not only transfers data but also preserves and transmits timing information. When the input/output device detects an access violation asynchronously, the timing data is captured and stored in the buffer alongside the data transfer, allowing the CPU to later correlate the violation timing with the corresponding task execution timing even though the detection occurred asynchronously.
Data Source
AI summary
An electronic control unit includes: a processor that executes a program; a memory that is enabled to be accessed by the processor; an access violation detection mechanism that monitors an access from the processor to the memory; and a time storage mechanism that stores detection time at which an access violation is detected by the access violation detection mechanism, in which the processor stores switching time at timing at which a task being executed is switched, the time storage mechanism stores the time at which the access violation is detected, and the processor identifies a task having caused the access violation by comparing the switching time and the detection time.