Monitoring voltage regulator switch activity reveals external power injection used in SPA or DPA attacks, enabling cryptographic shutdown.
Hardware-filtered threshold registers let multiple IC cores share one sensor while blocking unauthorized threshold changes and saving die area.
Dynamic LFSR-based obfuscation updates scan-chain keys during test access, blocking SAT, bypass, and scan-based attacks on protected circuits.
Configurable NoCs on separate chips use external and off-chip configuration data to enable flexible inter-chip communication with lower on-chip resource use.
Random masking and stored syndromes let a secure PUF subsystem correct noisy responses through a generic ECC processor without exposing raw secrets.
Balances internal verification requests with read/write traffic so dispersed storage nodes can check stored blocks without overloading memory access.
Tamper-triggered simultaneous erase of SONOS FPGA memory cells cuts erase time to one pulse while limiting leakage and blocking data extraction.
Ephemeral register fault counting separates attack-induced faults from SEUs in secure memory without added redundancy, speed loss, or power growth.
A kill switch clears PLD configuration data and decryption keys when threats are detected, blocking unauthorized access and side-channel attacks.
Encrypting only the compression dictionary cuts boot and pagination delays while preserving secure access to compressed digital data.