HBM Register Encryption for Secure Interface Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in protecting secure information transmitted over the interface bus between the host device and the memory device, as the host device can potentially monitor and interpret sensitive data intended for the memory device.
Innovation Solution
Implementing wrapper data registers (WDRs) with secure and non-secure compartments, coupled with cryptographic circuits for encryption and decryption, to ensure that secure information remains encrypted throughout its transmission and storage within the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If information is transmitted in plaintext over the interface bus, then ease of operation is improved, but data security deteriorates
Solution Approach 1:
A cryptographic circuit is introduced as an intermediary component between the interface bus and the secure circuit. This circuit automatically encrypts information before it reaches the secure circuit and decrypts it when needed, preventing the host device from accessing plaintext sensitive data while maintaining ease of operation. The cryptographic circuit acts as a mediator that handles the security complexity transparently.
2Object-affected harmful factors
If encryption is implemented for secure information, then data security is improved, but device complexity increases
Solution Approach 1:
The cryptographic circuit is merged with the existing interface bus structure and secure circuit architecture. The encryption and decryption functions are integrated into the data path without requiring separate standalone security modules, thereby improving data security while minimizing the increase in device complexity through consolidation of functions.
Data Source
AI summary
Embodiments of the disclosure are drawn to apparatuses, systems, and methods for signal encryption in high bandwidth memory. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.