Memory Interface Controller Switching for Concurrent NVM Access
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Solution Overview
Problem
Existing solutions for controlling access to non-volatile memory devices are costly due to the need for multiple memory banks and fail to efficiently prioritize access requests from multiple processing cores, leading to performance inefficiencies.
Innovation Solution
A system comprising a multiplexer and multiple memory interface controllers is used to selectively couple processing cores to non-volatile memories, allowing concurrent access and prioritization of read and write requests, thereby reducing design area and cost while enhancing processing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory banks are used to handle read and write requests concurrently, then processing throughput is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges multiple memory bank functions into a single non-volatile memory with unified address space, eliminating the need for separate memory banks while maintaining concurrent read-write capability through intelligent request management
Solution Approach 2:
The single non-volatile memory is designed to perform multiple functions (read operations, write operations, and execution-in-place) that were previously distributed across multiple specialized memory banks, reducing overall system complexity
2Device complexity
If a single non-volatile memory is used instead of multiple memory banks, then device complexity and cost are reduced, but access latency increases due to prioritization overhead
Solution Approach 1:
The system performs preliminary actions by pre-fetching data to intermediate buffers and pre-positioning memory pages before they are needed, reducing the actual access latency when read-write conflicts occur in the single non-volatile memory
Solution Approach 2:
The patent introduces intermediary structures (buffers and page management mechanisms) between the processing core and the single non-volatile memory, allowing prioritization of requests without directly blocking access to the memory itself
3Productivity
If multiple memory banks are implemented with execute-in-place capability, then processing efficiency is improved, but cost and device complexity increase significantly
Solution Approach 1:
The single non-volatile memory is designed to universally handle all types of operations (reading, writing, and execution-in-place) that were previously distributed across multiple specialized memory banks, achieving the same processing efficiency with reduced complexity
Data Source
AI summary
Various examples disclosed herein relate to controlling access to non-volatile memory devices. In an example embodiment, a device is provided. The device includes a first memory interface controller, a second memory interface controller, a multiplexer coupled to the first and second memory interface controllers, and a processing core coupled to the first and second memory interface controllers and to the multiplexer. The multiplexer is configured to selectably couple a first of the first and second memory interface controllers to a first memory and to selectably couple a second of the first and second interface controllers to a second memory. The processing core is configured to cause the multiplexer to selectably couple the first of the first and second memory interface controllers to the first memory and to selectably couple the second of the first and second memory interface controllers to the second memory.