Encoded Lock Bit Bus Architecture for Tamper-Resistant IC Transfer
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Solution Overview
Problem
Existing integrated circuit designs require a wide bus for secure lock bit transfer, which is inefficient and impractical due to large physical separation between flash storage and controller circuits, and reducing tamper resistance to decrease die area makes it easier to probe and unlock operations.
Innovation Solution
A tamper-resistant bus architecture that encodes security lock bits to minimize bus wires and circuitry, using a Hamming code to maintain security with a variable Hamming distance, and incorporates a decoder and inverters to prevent unlocking with fewer wire probes, along with an encode control bus and flag signals to detect tampering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wide bus is used to transmit security lock information from flash storage to controller, then security is maintained with sufficient tamper resistance, but die area increases due to large physical separation between flash storage and controller circuits
Solution Approach 1:
The patent changes the parameter of bus width by encoding lock bits into a compressed format that requires fewer wires. Instead of using a wide bus with many individual lock bit wires, the invention encodes the same security information into a narrower bus format, reducing the number of wires needed while maintaining the security function.
Solution Approach 2:
The patent uses error detection and correction codes to create redundant representations of the lock bit information. By encoding the lock bits with error detection capabilities, the system can verify the integrity of the transmitted information without requiring a wide bus, thus reducing wire count while maintaining security against tampering.
2Area of stationary object
If the value of r (tamper resistance) is reduced to decrease die area, then fewer bus wires are required, but it becomes easier to force a new valid state on the bus through probing
Solution Approach 1:
The patent incorporates error detection feedback into the bus transmission system. The encoder adds check bits that provide feedback information about the integrity of the transmitted lock bit data. This allows the receiver to detect if probing or tampering has occurred, maintaining security even with a reduced number of wires.
Solution Approach 2:
The patent introduces error detection and correction codes as an intermediary layer between the lock bits and the bus transmission. This intermediary encoding scheme protects the underlying lock bit information, making it harder for probes to directly affect the security state even though fewer wires are used.
3Reliability
If a wide data path is used to transmit redundant lock bits to the controller, then tamper resistance is improved, but device complexity increases due to the large number of bus wires required
Solution Approach 1:
The patent changes the parameter of data representation by encoding lock bits into a compressed format. Instead of transmitting multiple redundant lock bits individually over a wide bus, the invention encodes them into a narrower format that reduces the bus width requirement while maintaining the cryptographic security function.
Solution Approach 2:
The patent uses error detection codes to create verified copies of the lock bit information during transmission. This encoding approach allows the system to maintain tamper resistance through verification capabilities rather than through a wide bus with many individual bit wires, thus reducing overall device complexity.
Data Source
AI summary
A tamper-resistant bus architecture for secure lock bit transfer in an integrated circuit includes a nonvolatile memory having an n-bit storage region for storing encoded lock bits, A plurality of read access circuits are coupled to the nonvolatile memory. An n-bit tamper-resistant bus is coupled to the read access circuits. A decoder is coupled to the tamper-resistant bus. A k-bit decoded lock signal bus is coupled to the decoder. A controller is coupled to the k-bit decoded lock signal bus.