SONOS FPGA Fast Erase Architecture for Tamper Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-security applications, existing FPGA devices face challenges in quickly erasing p-channel and n-channel memory transistors due to high voltages and leakage currents, which can allow tampering and data extraction, as the erase procedure is slow and requires multiple pulses, making it difficult to protect configuration memory from unauthorized access.
Innovation Solution
A method for fast data erasing in FPGAs with SONOS configuration memory cells involves detecting tampering, disconnecting VDD from the logic core, simultaneously programming n-channel devices and erasing p-channel devices in all cells, and reconnecting VDD after the erase process, using specific voltage applications to prevent switch leakage and achieve rapid memory state changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prior-art schemes are used to erase n-channel and p-channel transistors sequentially with high voltages, then complete erasure is achieved, but the process is slow and allows time for tampering and data extraction
Solution Approach 1:
The patent merges the erasure operations of n-channel and p-channel transistors into a single simultaneous operation. By applying specific voltages to gates and wells together, both transistor types are erased at the same time, reducing the total erasure time from sequential multi-step processes to a single coordinated action that prevents tampering windows.
Solution Approach 2:
The patent applies preliminary voltage configuration to prepare the circuit state before erasure. By pre-setting the potentials on gates and wells according to the push-pull cell configuration, the system ensures that when erasure voltages are applied, both transistor types respond simultaneously and correctly, eliminating the need for sequential preparation steps.
2Reliability
If high voltages are applied to erase n-channel transistors, then erasure is achieved, but leakage current increases due to electron tunneling in switch transistors
Solution Approach 1:
The patent applies different voltage potentials to different regions (gates and wells) of the push-pull cell based on their specific requirements. By locally optimizing the voltage configuration for each transistor type and their associated wells, the system achieves effective erasure while minimizing unnecessary high voltage exposure that would cause leakage current and energy loss.
3Loss of energy
If multiple erase steps are used for n-channel devices, then leakage is reduced, but erasure time increases significantly
Solution Approach 1:
The patent combines multiple erasure steps into a single simultaneous operation by coordinating voltage applications to both n-channel and p-channel transistors together. This merging approach eliminates the need for separate erase sequences while maintaining control over leakage current through proper voltage potential management on gates and wells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables rapid erasure of all memory transistors in a single pulse, preventing data extraction and ensuring security by making the FPGA inoperable quickly, reducing the risk of tampering and data exposure, and minimizing residual effects through additional voltage threshold adjustments.
Implementation Method 1
This large current draw is due to the electron tunneling gate leakage on the switch transistor that occurs from the approximately 3V appearing on the gates of the switch transistors
Data Source
AI summary
A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power from the programmable logic core, and simultaneously programming the n-channel device and erasing the p-channel device in all cells.