Secure Memory Fault Detection Using Ephemeral Register Counting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Secure memory devices, such as smart cards, face challenges in distinguishing between fault attacks and single event upsets (SEUs), with existing methods either being inefficient or increasing power consumption and device size.
Innovation Solution
A method involving ephemeral registers with shorter data retention times, where payload data is initialized and a count value is incremented based on detected faults, using error detection codes to differentiate between fault attacks and SEUs, allowing for selective initialization and termination of processing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If time redundancy or hardware redundancy schemes are used to distinguish fault attacks from SEUs, then reliability is improved, but device complexity, speed, and power consumption are worsened
Solution Approach 1:
The patent changes the parameter of data retention time by using ephemeral registers with shorter retention times compared to traditional redundancy schemes. This allows the system to distinguish between fault attacks (which occur rapidly) and SEUs (which occur sporadically) by monitoring fault frequency within a shorter time window, thereby improving reliability without adding complex redundancy structures
Solution Approach 2:
The patent replaces the mechanical/hardware redundancy approach with a software-based fault detection mechanism. Instead of using duplicate hardware components or time-redundant operations, the system uses a fault detection unit that monitors and counts faults in real-time, comparing the count against a threshold to determine whether to terminate processing. This substitution reduces device complexity while maintaining or improving reliability
2Reliability
If fault detection mechanisms are added to secure memory devices, then reliability is improved, but operating speed is reduced
Solution Approach 1:
The patent implements preliminary action by pre-setting a threshold value for fault counting before processing begins. The fault detection unit continuously counts faults and automatically compares against this pre-established threshold, enabling rapid decision-making without requiring complex real-time analysis. This preliminary setup allows the system to maintain high processing speed while improving reliability through continuous fault monitoring
Solution Approach 2:
The patent applies the skipping principle by rapidly counting faults and quickly comparing the count against the threshold. When the threshold is exceeded, the system immediately terminates processing without delay. This rapid detection and response mechanism minimizes the time overhead of fault detection, thereby maintaining operating speed while improving reliability
3Reliability
If fault detection and counting is implemented continuously, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action through continuous fault counting with automatic threshold comparison. The fault detection unit operates continuously to count faults, but the system only triggers a response (processing termination) when the count exceeds the predetermined threshold. This periodic monitoring approach with a clear trigger point allows for reliable fault detection while minimizing unnecessary power consumption that would result from constant active response mechanisms
Data Source
AI summary
In a method of detecting a fault attack in a secure memory device, payload data is initialized by determining whether the payload data is consistent. The payload data is stored in a plurality of ephemeral registers included in the secure memory device. A count value included in the payload data is increased by detecting whether a fault is injected in the secure memory device from outside, during a processing operation of secure data, stored in the secure memory device. It is determined whether the fault injected in the secure memory device from the outside is caused by the fault attack based on the count value and a threshold value.