VMID-Based HSM Access Isolation in Multi-Core Processing
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Solution Overview
Problem
Multi-core processing systems face challenges in managing access rights and security for virtual machines, particularly in automotive applications, where complex functionalities and tight execution conditions require flexible configurations and secure isolation of hardware components like Hardware Secure Modules (HSMs).
Innovation Solution
A processing system with hardware address protection using a Virtual Machine ID (VMID) to filter requests and integrate a Hardware Secure Module (HSM) for cryptographic services, ensuring secure communication and access control between processing cores and the HSM through dedicated communication channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware address protection is implemented to limit access to physical addresses, then security and isolation are improved, but device complexity increases
Solution Approach 1:
The patent introduces a hardware address protection mechanism that acts as an intermediary between processing cores and physical addresses. This mechanism includes address translation tables and protection bits that mediate access requests, filtering them based on virtual machine identity and authorized address ranges. The intermediary layer provides security without requiring fundamental changes to the core processing architecture.
Solution Approach 2:
The address space is segmented into authorized and unauthorized ranges for each virtual machine. The hardware address protection divides the physical address space into multiple protected regions, each accessible only by specific virtual machines. This segmentation allows multiple VMs to coexist securely with isolated access rights to different memory and resource regions.
2Adaptability or versatility
If multiple virtual machines are supported with isolated access rights, then adaptability is improved, but device complexity increases
Solution Approach 1:
The hardware address protection mechanism is designed as a universal solution that supports multiple virtual machines simultaneously. The same address translation and protection infrastructure serves all VMs, with each VM configured through software-loaded tables rather than dedicated hardware per VM. This multi-functional approach allows the system to adapt to different numbers and configurations of virtual machines without proportionally increasing hardware complexity.
Solution Approach 2:
The address translation tables and access rights are dynamically configurable through software rather than fixed in hardware. The hypervisor or operating system can load different address protection configurations for different virtual machines, enabling the system to adapt its behavior based on runtime requirements. This dynamic configuration allows flexible VM creation, deletion, and migration without hardware reconfiguration.
3Reliability
If hardware secure module is isolated with dedicated communication channels, then security is improved, but device complexity increases
Solution Approach 1:
The hardware secure module is extracted as a separate, isolated component with dedicated communication channels. The HSM is physically separated from the main processing cores and communicates through specialized interfaces that enforce security policies. This extraction provides strong security isolation for cryptographic operations while keeping the main processing system simpler and more flexible.
Data Source
AI summary
A processing system includes a hardware address protection for limiting access to communication system addresses based on a virtual machine ID (VMID), a plurality of processing cores, a volatile memory, a hardware secure module (HSM), and a further communication system connecting the HSM to the communication system. A slave interface circuit of the further communication system receives a write request from the communication system and transmits the VMID in the write request to the HSM. The HSM accesses virtual machine configuration data to determine address data indicating positions of first and second memory areas in the volatile memory, and sends, via a master interface circuit, read/write requests, including the VMID, to the communication system to read command data from the first memory area and write response data to the second memory area. The HSM then stores a response notification to a register of the further communication system.