EDC Calculation Circuit for Reordered Blu-ray Recording Data
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Solution Overview
Problem
The existing Blu-ray disc recording technology faces challenges in achieving high-speed data recording due to the need to read and rearrange user data from the user data direction to the recording frame direction, which requires accessing the data buffer multiple times for error detecting code calculation and data rearrangement, leading to reduced memory access throughput.
Innovation Solution
An error detecting code calculation circuit is introduced that processes data in units of data groups, using a first operation section to calculate an error detecting code intermediate value from part of the user data and a second operation section to calculate the final error detecting code from the remaining data, allowing for reduced access to the data buffer by performing operations on only a portion of the code string.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If error detecting code calculation is performed on the entire user data code string, then the error detecting code accuracy is improved, but the data buffer access time increases
Solution Approach 1:
The user data code string is divided into multiple data groups, where each data group contains a portion of the user data. The error detecting code calculation is performed on each data group independently and in parallel, rather than processing the entire code string sequentially. This segmentation reduces the amount of data that needs to be accessed from the buffer at any one time, thereby reducing access time while maintaining code accuracy through independent calculation on each segment.
Solution Approach 2:
Instead of calculating the error detecting code for the entire user data code string at once, the system performs partial calculations on individual data groups. Each data group's error detecting code is calculated independently based on only that group's user data, which is a partial action compared to processing the whole. This partial processing approach reduces buffer access requirements while still providing comprehensive error detection coverage across all data groups.
2Adaptability or versatility
If data is rearranged from user data direction to recording frame direction, then the recording compatibility is improved, but the memory access throughput decreases
Solution Approach 1:
The data rearrangement process is segmented by processing individual data groups independently. Each data group is rearranged from user data direction to recording frame direction separately, allowing parallel processing of multiple segments. This segmentation enables the system to maintain recording compatibility through proper directional transformation while improving overall throughput by avoiding sequential processing of the entire data set.
Solution Approach 2:
The data groups are prepared and organized in advance before the actual rearrangement operation. By pre-organizing the data into manageable groups with clear directional relationships, the system reduces the complexity of the rearrangement process and enables more efficient memory access patterns, thereby improving throughput while maintaining the required recording frame direction compatibility.
Data Source
AI summary
The recording apparatus adds EDC to user data and transfers the EDC-added data to the scrambler in a sequence different from the coding direction Q. Though the processing data is added at an end in the direction Q, it is inserted at middle in the different sequence. Therefore, in order to transfer the EDC-added data in the different sequence, the EDC generator calculates an EDC intermediate value from an expected value of a latter part of an even number sector. Then, the EDC generator receives the user data in the different sequence and calculates EDC from expected values of the first half of the even number sector and an odd number sector and the EDC intermediate value. The expected value is an error detecting value of code string that has the same number of bits as the EDC-added data and a corresponding bit in the sequence of the direction Q is 1 and other bits are 0.