Edge Capacitive Coupling for Low-Loss Quantum Chip Links
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Solution Overview
Problem
Quantum computing chips face challenges in connecting qubits due to high susceptibility to interference and the need for low-loss connections, which are difficult to achieve with conventional dielectric materials.
Innovation Solution
The implementation of edge-based capacitive coupling between quantum computing chips using superconducting metal signal lines, which creates a capacitive bus connection that maintains qubit state integrity and reduces signal loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials are used for connecting qubits between chips, then electrical connection is achieved, but signal loss increases and qubit state integrity is destroyed
Solution Approach 1:
The patent removes the dielectric material from the qubit connection path entirely. By using direct superconducting metal-to-metal contact between chips, the lossy dielectric is extracted from the system, eliminating the primary source of signal loss and qubit state degradation while maintaining electrical connection functionality.
Solution Approach 2:
The patent introduces superconducting metal as an intermediary connection medium between qubits on different chips. This superconducting intermediary provides a low-loss transmission path that maintains qubit state integrity, replacing the harmful dielectric material while enabling the necessary electrical connection.
2Loss of energy
If dielectric material with low loss tangent is used, then signal loss is reduced, but material availability becomes impractical
Solution Approach 1:
The patent replaces scarce, expensive low-loss dielectric materials with abundant, easily manufacturable superconducting metals. The superconducting metal interconnects are standard components in quantum chip fabrication, making the solution practically manufacturable without relying on rare materials with extremely low loss tangents.
Solution Approach 2:
The patent changes the fundamental parameter of the connection medium from dielectric (insulating) material to superconducting (conducting) material. This parameter change transforms the connection from a lossy capacitive coupling through dielectric to a low-loss direct superconducting path, achieving both low signal loss and practical manufacturability.
3Productivity
If qubit circuits are connected to maintain quantum state, then quantum computing functionality is achieved, but susceptibility to environmental interference increases
Solution Approach 1:
The patent converts the potential harm of direct inter-chip connections (which could introduce interference) into a benefit by using superconducting metals. The superconducting property provides inherent shielding and low-loss transmission, converting what could be a vulnerable connection into a protected, high-fidelity quantum state transmission path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances quantum computing efficiency by allowing for more qubits to be transmitted between quantum computing elements while maintaining the integrity of the qubit state, thus overcoming the limitations of conventional connections.
Implementation Method 1
The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip
Implementation Method 2
edge-based capacitive coupling between quantum computing chips using superconducting metal signal lines
Data Source
AI summary
A quantum computing chip device provides an edge based capacitive, intra-chip connection. A first chip includes a first signal line with a distal end positioned proximate to or on an edge of the first chip and a proximal end positioned away from the edge of the first chip. A second chip includes a second signal line with a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip. The first signal line and the second signal line are configured to conduct a signal. The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip.