Edge Chip Pattern Prevention in Semiconductor Devices
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Solution Overview
Problem
The formation of patterns on edge chips in semiconductor devices is prone to damage, leading to surface steps that complicate planarization and potentially cause failures in main chips, as existing methods struggle to prevent pattern formation on edge chips effectively.
Innovation Solution
A method involving the formation of a molding layer and a supporter layer on a substrate with an etch stop layer, where edge blocking layers are used to prevent pattern formation on edge chips, allowing for the creation of a semiconductor device with minimized stepped surfaces and excellent electrical characteristics, involving multiple mask layers and etching processes to control the formation of electrodes and insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a recessed region is formed by etching on the edge chip to prevent pattern formation, then pattern damage is prevented, but the surface step between edge chip and main chip increases making planarization difficult
Solution Approach 1:
The patent applies preliminary action by forming the edge blocking layer before pattern formation to prevent pattern damage in advance. The edge blocking layer is deposited on the edge chip surface before any etching or patterning occurs, creating a protective barrier that prevents pattern formation on the edge chip while maintaining surface planarity for subsequent planarization processes
Solution Approach 2:
The edge blocking layer acts as an intermediary substance between the edge chip surface and the patterning process. This intermediate layer selectively blocks pattern formation on the edge chip while allowing normal processing on the main chip, and its material properties are chosen to be compatible with subsequent planarization operations
2Manufacturing precision
If no edge protection is applied, then planarization is easier, but pattern damage occurs on edge chips causing main chip failure
Solution Approach 1:
The patent applies local quality by making the edge blocking layer selective to the edge chip region only. The edge blocking layer is formed with spatial selectivity, covering only the edge chip surface while leaving the main chip exposed for normal patterning. This localized application prevents pattern damage at the edge regions without interfering with the planarization process across the entire substrate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively limits pattern formation on edge chips, reducing surface steps and enhancing planarization, thereby improving the electrical characteristics and reliability of semiconductor devices.
Implementation Method 1
A mask pattern is formed on the substrate. The forming the mask pattern includes etching the mask layer. A hole passing through the supporter layer, the molding layer and the etch stop layer is formed using the mask pattern as an etching mask.
Implementation Method 2
The interlayer insulating layer is planarized. Upper ends of the supporter layer and the hole on the first cell region, an upper end of the supporter layer on the first peripheral region, an upper end of the supporter layer on the second cell region, and an upper end of the supporter layer on the second peripheral region are formed at substantially the same level.
Data Source
AI summary
A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.