Edge-Coupled PCB Assembly for Quantum Processor Packaging
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Solution Overview
Problem
Existing packaging technologies for superconducting quantum processors, such as ball grid array packages, face challenges in scalability and footprint minimization, leading to increased bulk and unused solder balls, which are undesirable for cryogenic applications.
Innovation Solution
A printed circuit board assembly that edge-couples to an integrated circuit using coaxial connectors, minimizing unused solder balls and allowing for wire bonding, thereby reducing bulk and conserving space, while maintaining efficient electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ball grid array packaging is used to electrically couple a superconducting quantum processor to a PCB, then electrical connection is established, but the footprint and bulk increase significantly with the number of qubits
Solution Approach 1:
The patent transitions from a two-dimensional ball grid array layout to a three-dimensional stacked configuration. Multiple PCBs are stacked vertically with conductive traces extending through vias to connect qubits on different layers, enabling spatial efficiency by utilizing the vertical dimension rather than expanding horizontally.
Solution Approach 2:
The patent implements a nested structure where multiple PCBs are stacked within a compact footprint. Each PCB contains qubits and conductive traces, and the stack is enclosed within a cryostat. This nesting approach allows multiple functional layers to occupy the same horizontal space, reducing the overall footprint.
2Productivity
If the number of qubits and superconducting components increases, then processing capability improves, but the surface area and packaging bulk scale up accordingly
Solution Approach 1:
The patent addresses scaling by moving from planar expansion to vertical stacking. As the number of qubits increases, additional PCBs are stacked vertically rather than spreading out horizontally. This dimensional transition allows processing capability to scale while packaging bulk remains constrained in the vertical direction within the cryostat.
Solution Approach 2:
The patent divides the quantum processor into multiple discrete PCB segments, each containing a subset of qubits and conductive traces. This segmentation allows independent fabrication and assembly of smaller units that can be stacked and combined to achieve the desired total qubit count, managing complexity and packaging volume.
3Object-affected harmful factors
If conductive traces and shields are added to enclose signal paths, then noise mitigation improves, but the footprint and complexity increase
Solution Approach 1:
The patent combines multiple functions into integrated PCB structures. Conductive traces for signal transmission and shields for noise mitigation are merged into a unified multi-layer PCB design. Ground planes and shielding layers are integrated directly into the PCB stack, eliminating the need for separate external shielding components and reducing overall structural complexity.
Data Source
AI summary
Systems, methods, and devices for electrically coupling an integrated circuit to a set of coaxial lines via a printed circuit board assembly are described. A device sample holder includes a printed circuit board that is operable to edge-couple to an integrated circuit. A surface of the printed circuit board that carries a set of coaxial connectors is orthogonal to another surface of the printed circuit board that exposes a set of conductive traces. The set of conductive traces are operable to electrically couple to a set of conductive paths of an integrated circuit to provide a communicative path between the integrated circuit and components of an input/output system in a refrigerated environment.