Edge Memory Array Mat Sense Amplifier Placement
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Solution Overview
Problem
In dynamic random-access memory (DRAM) device arrays, the edge memory array mats have unused memory cells due to interleaved row segments, where only half of the memory cells are utilized, leading to inefficient use of memory space.
Innovation Solution
The edge memory array mats in a stacked or 3D memory array are configured to use all memory cells by splitting digit lines into complementary pairs and coupling them to sense amplifiers, allowing for continuous extension across the edge to connect with inner memory array mats, thereby enabling all memory cells to store and access data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If interleaved row segments are used in edge memory array mats, then manufacturing simplicity is maintained, but memory cell utilization efficiency deteriorates (only half of memory cells are used)
Solution Approach 1:
The memory array is divided into inner array mats and edge array mats, with further segmentation into first and second row segment sections. This segmentation allows different configurations: inner mats use traditional interleaved patterns while edge mats are configured to utilize all memory cells by connecting sense amplifiers to both row segment sections, thereby resolving the contradiction between manufacturing simplicity and memory cell utilization efficiency.
2Stability of the object's composition
If border row segments are included in edge memory array mats, then array continuity is maintained, but memory space efficiency deteriorates (significant areas are consumed by unused memory cells)
Solution Approach 1:
The border row segments in edge memory array mats are configured to serve dual purposes: maintaining array continuity and serving as active memory storage. By connecting sense amplifiers to both the first and second row segment sections in edge mats, the border segments become functional memory cells rather than unused areas, achieving both array continuity and improved memory space efficiency.
3Device complexity
If only half of memory cells in border row segments are used, then circuit complexity is reduced, but memory density deteriorates
Solution Approach 1:
The patent extends the circuit connectivity in the horizontal dimension by connecting sense amplifiers to both row segment sections (first and second) in edge memory array mats. This dimensional extension allows all memory cells including border segments to be utilized, thereby increasing memory density without proportionally increasing circuit complexity through the use of shared sense amplifier banks.
Data Source
AI summary
An edge memory array mat with access lines that are split, and a bank of sense amplifiers formed under the edge memory array may in a region that separates the access line segment halves. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes access line connectors configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.