Edge-Based Phase Frequency Detector for Low-Jitter 1 GHz Operation
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Solution Overview
Problem
Conventional Phase Frequency Detectors (PFDs) in wireline/wireless receivers suffer from high jitter, power consumption, and limited high-frequency performance due to complex logic gate configurations, which hinder precise data sampling at frequencies above 350 MHz.
Innovation Solution
An edge generation-based phase frequency detector (PFD) utilizing SR latches, NAND and NOR gates, and inverters to minimize gate count and reduce noise, with a streamlined design that operates at frequencies up to 1 GHz, reducing duty cycle and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PFD uses 4 latches and NAND gates for phase detection, then phase detection function is achieved, but jitter and power consumption increase significantly
Solution Approach 1:
The patent extracts and removes unnecessary logic gates from the conventional PFD structure. By eliminating redundant NAND gates and simplifying the latch configuration, the design achieves phase detection functionality with fewer components, directly reducing jitter and power consumption while maintaining detection accuracy.
Solution Approach 2:
The patent merges the functionality of multiple separate components into a more integrated structure. By combining phase detection and frequency detection functions into a unified PFD architecture with optimized latch connections, the design reduces the total gate count and minimizes the harmful effects of complex logic paths.
2Reliability
If conventional PFD uses extended reset path with multiple gates, then reset functionality is achieved, but high-frequency performance is limited to 350 MHz
Solution Approach 1:
The patent removes unnecessary gates from the reset path, extracting only the essential reset functionality. This simplification reduces the propagation delay in the reset path, enabling the PFD to operate at higher frequencies beyond the conventional 350 MHz limit while maintaining reliable reset operation.
Solution Approach 2:
The patent inverts the conventional approach to reset path design by using a more direct reset mechanism that avoids the traditional multi-gate configuration. This inverted architecture reduces the critical path delay, allowing the circuit to respond faster and operate at higher frequencies.
3Ease of operation
If additional components like XOR gates or inverters are added to generate complementary signals, then signal generation is achieved, but device complexity and reference spurs increase
Solution Approach 1:
The patent merges the complementary signal generation function into the existing latch structure. By utilizing the natural complementary outputs of the SR latches and optimizing their interconnection, the design generates both up and down signals without requiring additional XOR gates or inverters, thus reducing device complexity and minimizing reference spurs.
Solution Approach 2:
The patent makes the latch outputs serve multiple functions simultaneously. The same latch outputs that provide phase detection information also directly provide the complementary signals needed for frequency detection and charge pump control, eliminating the need for separate signal generation components.
Data Source
AI summary
A circuit for an edge-based Phase Frequency Detector (PFD) (200) comprising two edge detectors (103), two SR latches (104), one NAND gate (106), and one NOR gate (107). A reference (Ref) (101) and feedback signals (Fb) (102) are provided to the two edge detector (103) which generates a pulse of active low logic. The output of the edge detector (103) is provided to the two SR latches (104), which provide output signals of the phase frequency detectors. The output of two SR latch (104) is buffered though two invertors (201) and additionally connected to a pair of cross-coupled inverters (202) to generate complementary up (UP and UPb) and down (DN and DNb) signals (105). Phase Frequency Detector (PFD) circuit (200) minimize the number of gates, reducing noise and Random Jitter (RJ), enhance dead zone performance and also reduce the duty cycle of the reference (Ref) (101) and feedback (Fb) signal (102) to a minimal 10%.