EDMOS Gate Dielectric Layout for High Breakdown and Low On-Resistance
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Solution Overview
Problem
Extended drain metal oxide semiconductor (EDMOS) transistors have higher on-resistance compared to lateral double-diffused MOS (LDMOS) transistors and require fewer fabricating steps, necessitating improved performance with existing semiconductor materials.
Innovation Solution
The EDMOS transistor design includes a substrate with a gate, source, and drain doped regions, featuring a thin gate dielectric layer under the gate and a thicker gate dielectric layer extending to the drain doped region, along with multiple well and doped regions, to enhance breakdown voltage and current capacity, while reducing fabricating steps by using a thick gate dielectric layer to fill the gap between the gate and drain, thus supporting higher voltage and lower voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a drift region with low doping concentration is provided between the drain doped region and the channel to increase breakdown voltage, then the breakdown voltage is improved, but the on-resistance increases
Solution Approach 1:
The gate dielectric layer is segmented into two distinct thickness regions: a first thickness region closer to the source doped region and a second thickness region closer to the drain doped region. The second thickness region is greater than the first thickness region. This segmentation allows the device to have different dielectric thicknesses in different regions, enabling optimized electric field distribution that simultaneously achieves high breakdown voltage and low on-resistance without requiring a low-doping drift region.
Solution Approach 2:
Different regions of the gate dielectric layer are assigned different thicknesses to serve different functions. The thinner first thickness region reduces resistance in the source region, while the thicker second thickness region increases breakdown voltage in the drain region. This local quality variation allows each region to be optimized for its specific function, resolving the contradiction between breakdown voltage and on-resistance.
2Reliability
If the gate dielectric layer thickness is increased to enhance breakdown voltage, then the breakdown voltage is improved, but the current capacity decreases
Solution Approach 1:
The gate dielectric layer is designed with non-uniform thickness where the first thickness region (closer to source) is thinner and the second thickness region (closer to drain) is thicker. The thinner first thickness region maintains good current capacity by reducing resistance, while the thicker second thickness region provides high breakdown voltage. This local quality differentiation resolves the contradiction between breakdown voltage and current capacity.
3Reliability
If traditional LDMOS transistor structure with drift region is used to achieve high breakdown voltage, then the breakdown voltage is improved, but the number of fabricating steps increases
Solution Approach 1:
The invention merges the breakdown voltage enhancement function and the gate dielectric layer into a single integrated structure. Instead of adding a separate drift region as in traditional LDMOS, the gate dielectric layer itself is designed with varying thickness to provide both gate control and breakdown voltage enhancement. This merging eliminates the need for additional drift region fabrication steps, reducing device complexity while maintaining high breakdown voltage.
Data Source
AI summary
An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.