Embedded Die Substrate Segmentation for Yield and Warpage Control
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Solution Overview
Problem
Traditional embedded die substrate (EDS) packages face challenges such as low yield, high cost, and limited design flexibility due to manufacturing defects and the need for precise substrate formation around semiconductor dies, leading to wastage of both substrates and semiconductor components.
Innovation Solution
The method involves forming top and bottom substrate submodules with embedded semiconductor components, allowing for flexible design and increased yield by testing and discarding defective components before assembly, and using encapsulants to integrate these submodules into a single EDS with alternative interconnect structures like conductive pillars or bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional substrate formation around semiconductor die is used, then substrate structural support is provided, but manufacturing yield is low and cost is high due to defects and wastage
Solution Approach 1:
The substrate is divided into multiple laminated layers that can be separately manufactured and assembled. This segmentation allows defective layers to be identified and replaced without wasting the entire substrate or embedded semiconductor components, thereby improving manufacturing yield and reducing material wastage.
Solution Approach 2:
Semiconductor components are embedded into the substrate layers during the lamination process before final assembly. This preliminary embedding allows for testing and identification of defective components early in the manufacturing process, enabling replacement without wasting finished substrates or components.
2Adaptability or versatility
If precise substrate formation around semiconductor die is required, then proper electrical interconnect is achieved, but design flexibility is limited
Solution Approach 1:
The substrate is segmented into multiple laminated layers with conductive traces and vias formed in each layer. This segmentation provides flexibility in routing electrical interconnects while maintaining precise connections, as each layer can be independently designed and optimized for specific electrical pathways.
Solution Approach 2:
Electrical interconnect is achieved not only in the planar dimension but also through the vertical dimension using conductive vias that pass through multiple laminated layers. This multi-dimensional approach provides design flexibility in routing while maintaining precise electrical connections.
3Adaptability or versatility
If semiconductor die are embedded during substrate formation, then three dimensional packaging is achieved, but substrate options are limited
Solution Approach 1:
The substrate is divided into multiple laminated layers that can be manufactured using different materials and processes. This segmentation expands substrate design options as each layer can be optimized for specific requirements, while the lamination process manages the complexity of embedding semiconductor components.
Solution Approach 2:
The lamination process serves multiple functions: it provides structural support, creates electrical interconnect through conductive traces and vias, and enables embedding of semiconductor components. This multi-functionality reduces device complexity by consolidating multiple processes into a single lamination step.
Data Source
AI summary
A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.