EEPROM Read Amplifier Leakage Reduction via Substrate Effect
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Solution Overview
Problem
Current EEPROM memory technologies face challenges in reducing the size of memory cells due to current leaks caused by short-channel effects and electron diffusion between neighboring bit lines, leading to instabilities and read errors, which limit the compactness and accuracy of memory planes.
Innovation Solution
The solution involves a read amplifier configuration with a pre-charge voltage and a source voltage higher than the pre-charge voltage applied to the floating-gate transistor, utilizing a substrate effect to increase the potential barrier and reduce leakage currents, and incorporating a feedback loop to maintain the input voltage of the read amplifier above the pre-charge voltage, especially for erased cells, to prevent voltage drops and enhance read current accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase density, then memory plane density is improved, but current leaks increase due to short-channel effects and electron diffusion
Solution Approach 1:
The patent applies preliminary anti-action by pre-charging the bit line to a specific voltage level before the read operation and using a read amplifier that actively compensates for voltage drops. This preliminary preparation counteracts the harmful effects of current leaks during the read operation, allowing smaller memory cells to be used without suffering from increased leakage currents.
Solution Approach 2:
The patent changes the voltage parameters during the read operation. Specifically, it uses a read amplifier that can maintain the bit line voltage above a threshold level despite current leaks, and applies different voltages to control gates during read versus program/erase operations. This parameter adjustment allows the memory cell to operate reliably at smaller dimensions where short-channel effects are more pronounced.
2Device complexity
If conventional read amplifier configuration is used, then device simplicity is maintained, but read accuracy deteriorates due to voltage drops and current leaks
Solution Approach 1:
The patent implements feedback by using a read amplifier that continuously monitors the voltage on the bit line and actively adjusts its operation to maintain the voltage above a threshold level. This feedback mechanism compensates for voltage drops caused by current leaks, ensuring accurate read operations even in scaled-down memory cells where leakage is more significant.
Solution Approach 2:
The patent applies preliminary action by pre-charging the bit line to a specific voltage level before the read operation begins. This preliminary charging ensures that even if current leaks occur during the read operation, the voltage remains sufficient to maintain accurate reading, thus improving measurement precision without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces current leaks, allowing for the creation of smaller, more compact memory cells with improved read accuracy and reduced surface area, increasing the density of memory planes while minimizing read errors.
Implementation Method 1
utilizing a substrate effect to increase the potential barrier and reduce leakage currents
Data Source
AI summary
A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.