EEPROM Readout Circuit Self-Detection Charging Control
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Solution Overview
Problem
Current readout circuits in EEPROMs suffer from false charging and slow reading speeds due to the lack of a detection circuit, leading to increased susceptibility to manufacturing process drifts and inefficiencies as the number of readout circuits increases.
Innovation Solution
Incorporating a self-detection circuit with a precharge circuit, control circuit, and detection logic gates (NOT gates, NAND gates, and triggers) to monitor and control the charging process, ensuring accurate detection and faster charging times by using a P-type or N-type charge transistor and adjustable reference current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional readout circuit without detection circuit is used, then the circuit structure is simple, but false charging occurs and reading speed is slow
Solution Approach 1:
The patent implements a detection circuit that continuously monitors the charging state of the first node A and provides feedback signals to control the charging process. The detection circuit includes multiple NOT gates and NAND gates that detect voltage levels and generate control signals to prevent false charging and optimize reading speed by dynamically adjusting the charging process based on real-time circuit state
Solution Approach 2:
The detection circuit automatically detects the charging state and controls the charging process without external intervention. The circuit self-regulates by using its own output signals to control the charging transistor, eliminating the need for external control mechanisms and achieving both fast reading speed and prevention of false charging
2Quantity of substance
If the number of readout circuits increases to accommodate more memory digits, then memory capacity increases, but manufacturing process drift impact increases and circuit reliability decreases
Solution Approach 1:
The detection circuit provides real-time monitoring and feedback control for each readout circuit, ensuring that manufacturing process drifts do not propagate across multiple circuits. Each circuit independently detects and adjusts its charging parameters, maintaining consistent performance across the entire memory array even as the number of circuits increases
Solution Approach 2:
The patent uses parameter changes in the detection circuit to compensate for manufacturing drifts. By dynamically adjusting detection thresholds and control signal levels based on actual circuit behavior, the system maintains reliable operation across varying process conditions and large numbers of circuits
3Productivity
If charging time is reduced to increase reading speed, then productivity improves, but charging accuracy decreases and false charging increases
Solution Approach 1:
The detection circuit continuously monitors the charging voltage at node A and provides real-time feedback to control the charging transistor. This feedback mechanism allows the circuit to charge quickly while automatically detecting when the target voltage is reached, preventing both under-charging and false charging, thus maintaining high reading speed with high charging accuracy
Solution Approach 2:
The detection circuit is pre-configured with threshold detection capabilities that anticipate the charging completion point. By preparing the detection logic in advance and using predetermined voltage thresholds, the circuit can rapidly determine charging completion without sacrificing accuracy, enabling fast reading speeds while maintaining precise charging control
Data Source
AI summary
A readout circuit with a self-detection circuit and a control method therefor. The circuit comprises a pre-charging circuit and a control circuit, the pre-charging circuit and the control circuit being connected to a first node and used for charging a memory unit. The readout circuit also comprises a detection circuit, the detection circuit and the pre-charging circuit being connected to the first node. The detection circuit comprises a third NOT gate, a fourth NOT gate, a first NAND gate, a sixth NOT gate, a first trigger and an eighth NOT gate. In such a manner of detecting the reversal of the first NOT gate through the reversal of the third NOT gate, the charging duration of the first node (A) can be greatly reduced, thereby reducing the reading duration of the whole circuit. At the same time, the re-occurrence of a state of charging the circuit can be avoided after pre-charging has ended.